U.S. patent number 10,095,523 [Application Number 14/824,123] was granted by the patent office on 2018-10-09 for hardware counters to track utilization in a multithreading computer system.
This patent grant is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. The grantee listed for this patent is International Business Machines Corporation. Invention is credited to Jane H. Bartik, Jonathan D. Bradbury, Gary M. King, Daniel V. Rosa, Donald W. Schmidt.
United States Patent |
10,095,523 |
Bartik , et al. |
October 9, 2018 |
Hardware counters to track utilization in a multithreading computer
system
Abstract
Embodiments relate tracking utilization in a multithreading (MT)
computer system. According to one aspect, a computer system
includes a configuration with a core configured to operate in a MT
that supports multiple threads on shared resources of the core. The
core is configured to perform a method that includes resetting a
plurality of utilization counters. The utilization counters include
a plurality of sets of counters. During each clock cycle on the
core, a set of counters is selected from the plurality of sets of
counters. The selecting is based on a number of currently active
threads on the core. In addition, during each clock cycle a counter
in the selected set of counters is incremented based on an
aggregation of one or more execution events at the multiple threads
of the core. Values of the utilization counters are provided to a
software program.
Inventors: |
Bartik; Jane H. (Poughkeepsie,
NY), Bradbury; Jonathan D. (Poughkeepsie, NY), King; Gary
M. (Millbrook, NY), Rosa; Daniel V. (Highland, NY),
Schmidt; Donald W. (Stone Ridge, NY) |
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
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Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION (Armonk, NY)
|
Family
ID: |
52727110 |
Appl.
No.: |
14/824,123 |
Filed: |
August 12, 2015 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20150347150 A1 |
Dec 3, 2015 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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14226980 |
Mar 27, 2014 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F
9/3851 (20130101); G06F 9/3861 (20130101); G06F
9/30145 (20130101); G06F 1/10 (20130101); G06F
9/5061 (20130101); G06F 9/5083 (20130101) |
Current International
Class: |
G06F
9/38 (20180101); G06F 9/50 (20060101); G06F
1/10 (20060101); G06F 9/30 (20180101) |
References Cited
[Referenced By]
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Other References
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2017, 4 pages. cited by applicant.
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Primary Examiner: Petranek; Jacob A
Attorney, Agent or Firm: Cantor Colburn LLP
Parent Case Text
DOMESTIC PRIORITY
This application is a continuation of U.S. patent application Ser.
No. 14/226,980, filed Mar. 27, 2014, the content of which is
incorporated by reference herein in its entirety.
Claims
What is claimed is:
1. A computer implemented method for tracking utilization in a
configuration comprising a core configured to operate in a
multithreading (MT) mode, the MT mode supporting multiple threads
on shared resources of the core, the method comprising: resetting a
plurality of utilization counters, the utilization counters
comprising a plurality of sets of counters including a first set of
counters and a second set of counters, each set of counters
corresponding to a different number of currently active threads and
each set of counters non-overlapping with each other set of
counters; performing for each clock cycle on the core: selecting a
set of counters from the plurality of sets of counters, the
selecting based on a number of currently active threads on the core
and not based on which specific threads of the multiple threads are
currently active, wherein the first set of counters is selected
based on exactly one of the multiple threads being currently
active, and the second set of counters is selected based on exactly
two of the multiple threads being currently active; and
incrementing a counter in the selected set of counters, the
incrementing based on an aggregation of one or more execution
events at the multiple threads of the core; and providing values of
the utilization counters to a software program.
2. The method of claim 1, wherein the execution event includes a
clock cycle and the counter in the selected set of counters is
incremented by one.
3. The method of claim 2, wherein the execution event further
includes an instruction completion and an other counter in the
selected set of counters is incremented based on a number of
instruction completions on all of the currently active threads
during the clock cycle.
4. The method of claim 2, wherein the execution event further
includes a cache miss and an other counter in the selected set of
counters is incremented based on a number of cache misses on all of
the currently active threads during the clock cycle.
5. The method of claim 2, wherein the execution event further
includes a branch misprediction and an other counter in the
selected set of counters is incremented based on a number of branch
mispredictions on all of the currently active threads during the
clock cycle.
6. The method of claim 2, wherein a thread is currently active when
the thread is valid and not in a wait state.
7. The method of claim 1, wherein the software program is an
operating system or a hypervisor.
Description
BACKGROUND
The present invention relates generally to a computer system
supporting multiple threads, and more specifically, to hardware
counters to track utilization in a multithreading computer
system.
As processor speed of computer systems has increased over the past
decades, there has not been a proportional increase in the speed in
which the memory of such computer systems can be accessed. Thus,
the faster the processor's cycle time, the more pronounced is the
delay of waiting for data to be fetched from memory. The effects of
such delays have been mitigated by various levels of caching, and
in recent processors, by multithreading (MT).
MT allows various core resources of a processor to be shared by a
plurality of instruction streams known as threads. Core resources
can include instruction-execution units, caches,
translation-lookaside buffers (TLBs), and the like, which may be
collectively referred to generally as a core. During latency caused
by a cache-miss or other delay in one thread, one or more other
threads can utilize the core resources, thus increasing the
utilization of the core resources. In a super-scalar processor
simultaneous-multithreading (SMT) implementation, multiple threads
may be simultaneously serviced by the core resources of one or more
cores.
In contemporary hardware platforms, MT is typically implemented in
a manner that is transparent to an operating system (OS) that runs
on the MT hardware. One aspect of this characteristic is that the
OS does not require modification to utilize the MT hardware.
However, transparent MT operation with respect to the OS can result
in high variability of response time, capacity provisioning,
capacity planning, and billing. This variability can occur because
the OS is unaware of whether its tasks have exclusive control of a
core, or whether its tasks are executing as threads that share a
core. By design, the highest capacity for a memory-intensive
workload on MT-capable hardware is achievable when there is a high
average thread density when the cores are in use. Additional
capacity may be due to increased cache exploitation provided by MT.
If an OS does not consistently maintain high average thread
densities for utilized cores, then the additional overall
throughput capacity provided by MT will not be available. For
example, if the hardware runs a single MT thread per core when
there is low compute utilization and runs with high thread density
when there is high compute utilization, then it can be very
difficult to determine how much total MT compute capacity is
available to the workload. This hardware variability in the MT
thread exploitation can lead to variability in both transaction
response times and in billing in a similar fashion as previously
described with respect to capacity.
SUMMARY
Embodiments include a method, system, and computer program product
for tracking utilization in a multithreading (MT) computer system.
According to one aspect, a computer system includes a configuration
with a core configured to operate in a MT mode that supports
multiple threads on shared resources of the core. The core is
configured to perform a method that includes resetting a plurality
of utilization counters. The utilization counters include a
plurality of sets of counters. During each clock cycle on the core,
a set of counters is selected from the plurality of sets of
counters. The selecting is based on a number of currently active
threads on the core. In addition, during each clock cycle a counter
in the selected set of counters is incremented based on an
aggregation of one or more execution events at the multiple threads
of the core. Values of the utilization counters are provided to a
software program.
According to another aspect, a computer implemented method for
tracking utilization in a configuration is provided. The
configuration includes a core configured to operate in a
multithreading (MT) mode. The MT mode supports multiple threads on
shared resources of the core. The method includes resetting a
plurality of utilization counters. The utilization counters include
a plurality of sets of counters. During each clock cycle on the
core, a set of counters is selected from the plurality of sets of
counters. The selecting is based on a number of currently active
threads on the core. In addition, during each clock cycle a counter
in the selected set of counters is incremented based on an
aggregation of one or more execution events at the multiple threads
of the core. Values of the utilization counters are provided to a
software program.
According to a further aspect, a computer program product for
tracking utilization in a configuration is provided. The
configuration includes a core configured to operate in a
multithreading (MT) mode. The MT mode supports multiple threads on
shared resources of the core. The computer program product includes
a computer readable storage medium having program instructions
embodied therewith, wherein the computer readable storage medium is
not a signal, the program instructions readable by a processing
circuit to cause the processing circuit to perform a method. The
method includes resetting a plurality of utilization counters. The
utilization counters include a plurality of sets of counters.
During each clock cycle on the core, a set of counters is selected
from the plurality of sets of counters. The selecting is based on a
number of currently active threads on the core. In addition, during
each clock cycle a counter in the selected set of counters is
incremented based on an aggregation of one or more execution events
at the multiple threads of the core. Values of the utilization
counters are provided to a software program.
BRIEF DESCRIPTION OF THE DRAWINGS
The subject matter which is regarded as embodiments is particularly
pointed out and distinctly claimed in the claims at the conclusion
of the specification. The forgoing and other features, and
advantages of the embodiments are apparent from the following
detailed description taken in conjunction with the accompanying
drawings in which:
FIG. 1A depicts a computing environment that may be implemented in
accordance with an embodiment;
FIG. 1B depicts a computing environment that may be implemented in
accordance with an embodiment;
FIG. 2 depicts processing circuitry of a core that may be
implemented in accordance with an embodiment;
FIG. 3 depicts a computing environment that may be implemented in
accordance with an embodiment;
FIG. 4 depicts an example of hypervisor context retention in a
computing environment that may be implemented in accordance with an
embodiment;
FIG. 5 depicts a process flow for dynamic enablement of
multithreading in accordance with an embodiment;
FIG. 6A depicts an example of a CPU address expansion process in
accordance with an embodiment;
FIG. 6B depicts an example of a CPU address contraction process in
accordance with an embodiment;
FIG. 7 depicts a process flow for a set-multithreading order in
accordance with an embodiment;
FIG. 8 depicts an example of processing circuitry of a core that
may be implemented to track utilization in accordance with an
embodiment;
FIG. 9 depicts an example of a configuration that captures
utilization counters in accordance with an embodiment;
FIG. 10 depicts a process flow for tracking utilization in
accordance with an embodiment; and
FIG. 11 depicts a computer-readable medium according to an
embodiment.
DETAILED DESCRIPTION
Exemplary embodiments described herein provide performance
monitoring of multithreading (MT) operations in a computer system
that supports a single thread (ST) and a MT mode of operation. The
system described herein enables software to mitigate hardware
variability by requiring an operating system (OS) to explicitly
"opt in" to exploit MT hardware. When the OS understands the MT
nature of the execution environment, the OS has the ability to
explicitly manage thread densities per processor core (to the best
of its ability, given a workload dispatch pattern). The OS has the
option to maintain high thread densities even when compute
resources are less utilized, thereby mitigating much of the
variability in total compute capacity that may be seen on other MT
implementations. As a direct result of maintaining high thread
densities, both the transaction response times and billing aspects
may be more consistent. Multithreading value can be increased when
there are consistently high thread densities per processor
core.
In accordance with embodiments, in order to determine any missed
opportunity for capacity growth, the OS control program is provided
with the ability to query the machine for the number of
instructions executed and cycles that a particular core spent
running on one thread, two threads, and so on up to total number of
threads on the core. In embodiments, hardware counters are provided
to count events (e.g., number of instructions executed and number
of clock cycles) in the core at various thread densities (e.g., one
thread, two threads, etc.) and not on an individual thread or CPU
basis. The hardware counters which increment can vary based upon
how many threads are active in the core.
Software can obtain the information from the counters and use the
counter information to determine when there is missed opportunity
to execute more work on another thread of the core. From this
information, the software can also be able to determine what
percentage of the core resources were used by a single thread and
use this information for software chargeback. By aggregating all of
the information from the cores in a system, it is possible for the
OS to do capacity planning such as calculating total capacity, used
capacity, and free capacity.
As used herein, a logical thread refers to a single instruction
stream and its associated state. That is, at an architecture level,
each logical thread represents an independent central processing
unit (CPU) or processor. At a hardware level, a thread is the
execution of an instruction stream associated with a logical
thread, combined with the maintaining of that guest state, when the
thread is dispatched. Therefore, the terms "thread" and "CPU" may
be used interchangeably herein.
In an exemplary embodiment, a CPU contains sequencing and
processing facilities for instruction execution, interruption
action, timing functions, initial program loading, and other
machine-related functions. A CPU defines logical functions that may
map to a variety of underlying physical implementations. The CPU,
in executing instructions, can process binary integers and
floating-point numbers (e.g., binary, decimal, and hexadecimal) of
fixed length, decimal integers of variable length, and logical
information of either fixed or variable length. Processing may be
in parallel or in series. The width of processing elements,
multiplicity of shifting paths, and the degree of simultaneity in
performing different types of arithmetic can differ from one model
of CPU to another without affecting the logical results.
Instructions which the CPU executes can include a number of
instruction classes, such as: general, decimal,
floating-point-support (FPS), binary-floating-point (BFP),
decimal-floating-point (DFP), hexadecimal-floating-point (HFP),
control, and I/O instructions. The general instructions can be used
in performing binary-integer-arithmetic operations and logical,
branching, and other non-arithmetic operations. The decimal
instructions operate on data in decimal format. The BFP, DFP, and
HFP instructions operate on data in BFP, DFP, and HFP formats,
respectively, while the FPS instructions operate on floating-point
data independent of the format or convert from one format to
another. Privileged control instructions and the I/O instructions
can be executed when the CPU is in a supervisor state, and
semi-privileged control instructions can be executed in a problem
state, subject to appropriate authorization mechanisms.
The CPU provides registers which are available to programs but do
not have addressable representations in main storage. The registers
can include, for instance, a current program-status word (PSW),
general registers, floating-point registers and a
floating-point-control register, vector registers, control
registers, access registers, a prefix register, a time-of-day
(TOD)-programmable register, and registers for a clock comparator
and CPU timer. This set of registers may be referred to as the
CPU's architected register context. Each CPU in a configuration can
provide access to a TOD clock, which may be shared by all CPUs in
the configuration. An instruction operation code can determine
which type of register is to be used in an operation.
Each CPU may have a type attribute that indicates whether it
provides a full complement of functions and facilities (e.g., a
general CPU), or whether it is intended to process specific types
of workloads (e.g., a specialty CPU). A primary CPU is either a
general CPU or a CPU having the same type as the CPU started
following a last initial program load (IPL) operation (the IPL
CPU). A secondary CPU is any CPU other than a general CPU having a
CPU type that differs from the IPL CPU.
A multithreading facility may be available on a computer system
that implements a supporting architecture. The multithreading
facility provides support for multithreading to enable a group of
threads, which may also be referred to as CPUs, that share a core.
When the multithreading facility is enabled, the CPUs within a core
may share certain hardware resources such as execution units or
caches. When one CPU in a core is waiting for hardware resources
(typically, while waiting for a memory access), other CPUs in the
core can utilize the shared resources in the core rather than have
them remain idle. When the multithreading facility is installed and
enabled, a thread is synonymous with a CPU that is a member of a
core. When the multithreading facility is not installed, or the
facility is installed but not enabled, a core comprises a single
CPU or thread.
When the multithreading facility is installed, it may be enabled by
execution of a set-multithreading signal processor (SIGP) order. In
an exemplary embodiment, when the multithreading facility is
enabled, the number of CPUs in a configuration is increased by a
multiple, the value of which is determined by a program-specified
maximum thread identification (PSMTID). The number of CPUs in a
core can be one more than the PSMTID. A number of CPUs
corresponding to this multiple are grouped into a core. Each core
of the same CPU type in a configuration has the same number of
CPUs. Each CPU within a core is of the same CPU type; however,
based on the model and CPU type, some CPUs within a core may not be
operational.
In an exemplary embodiment, a control program, such as an operating
system (OS), explicitly enables multithreading in order for it to
be usable by the configuration that the OS manages. Alternatively,
a hypervisor can enable multithreading and guests of the hypervisor
and their applications can benefit transparently. An application
program is generally unaware of whether multithreading has been
enabled. When multithreading is enabled, the CPU addresses of all
CPUs in the configuration are adjusted to include a core
identification (or core ID) in the leftmost bits of the address and
a thread identification (thread ID, or TID) in the rightmost bits
of the address. The core ID may also be referred to as a core
address value, and the TID may be referred to as a thread address
value. CPUs within a core may share certain hardware facilities
such as execution units or lower-level caches, thus execution
within one CPU of a core may affect the performance of other CPUs
in the core.
In order to manage changes associated with dynamically switching
one or more cores of a configuration between single thread and
multithreading modes, a number of support features are included. To
maintain compatibility with programs that do not support
multithreading, a single thread mode may be the default mode upon a
reset or deactivation. Exemplary embodiments include features to
preserve, communicate, and restore thread context from the
multithreading mode to support analysis and/or restoration of the
thread context after transitioning from the multithreading mode to
the single thread mode.
A computing environment that may be implemented by an exemplary
embodiment can be based, for example, on the z/Architecture offered
by International Business Machines Corporation, Armonk, N.Y. The
z/Architecture is described in an IBM.RTM. publication entitled,
"z/Architecture Principles of Operation," IBM Publication No.
SA22-7832-09, August 2012, which is hereby incorporated herein by
reference in its entirety. In one example, a computing environment
based on the z/Architecture includes an eServer zSeries, offered by
International Business Machines Corporation, Armonk, N.Y. A
computing environment can include, for example, a processor complex
with one or more partitions (e.g., logical partitions) with one or
more cores (e.g., processor cores), and one or more levels of
hypervisors as further described herein.
FIG. 1A shows a computer system 100 as an example of a computing
environment that supports multithreading (MT). In the example of
FIG. 1A, the computer system 100 includes a plurality of processor
cores 102, an input/output (I/O) subsystem 104, and system memory
160. The I/O subsystem 104 can provide access to I/O devices known
in the art. The processor cores 102, also referred to simply as
"cores" herein, can include processing circuitry with supporting
elements. In the example of FIG. 1A, five cores 102 are depicted as
core1 110, core2 120, core3 130, core4 140, and cores 150; however,
a greater or fewer number of cores 102 is also contemplated. An MT
facility 103 may be a hardware component of each of the cores 102.
In this example, each of the cores 102 is capable of supporting up
to four threads. For instance, core1 110 can support threads 111,
112, 113, and 114. Core2 120 can support threads 121, 122, 123, and
124. Core3 130 can support threads 131, 132, 133, and 134. Core4
140 can support threads 141, 142, 143, and 144. Core5 150 can
support threads 151, 152, 153, and 154. Note that not all four
threads of each core 102 may be operational at any instant. For
example, in core3 130, threads 131 and 132 can be operational while
threads 133 and 134 are not operational (depicted with
shading).
FIG. 1A also depicts the system memory 160 of the computer system
100, where parts of the system memory 160 are apportioned to
logical partition1 (LPAR1) 170, LPAR2 180, and LPAR3 190. The LPARs
170, 180, 190 represent virtualized computing systems (also known
as configurations) in which an operating system such as Linux or
the IBM.RTM. z/OS.TM., z/VM, or zTPF operating system may be
executed. FIG. 1A also shows the apportionment of the cores 102 to
the LPARs 170, 180, 190. In this illustration, core1 110 and core2
120 are dedicated for use by LPAR1 170. Core3 130 is dedicated for
use by LPAR2 180, and cores 150 is dedicated for use by LPAR3 190.
Core4 140 may be shared between LPAR2 180 and LPAR3 190, but is
shown as being assigned to LPAR2 180 in FIG. 1A. LPAR3 190 shows an
example of two different types of cores 102 being employed by the
partition, where core4 140 allows multiple threads to be
operational, but cores 150 does not allow multiple threads to be
operational in this example. In the example of FIG. 1A, LPAR1 170
provides processing resources for OS 171 and programs 172, 173,
174, and 175. LPAR2 180 provides processing resources for OS 181
and programs 182, 183, and 184. LPAR4 190 provides processing
resources for OS 191 and programs 192 and 193.
Under control of an operating system executing in an LPAR, programs
are executed on the threads of a core. In an exemplary embodiment,
an individual thread executes only one program at time; however, a
program that is designed to be re-entrant may be executed on
multiple threads or cores simultaneously. For example, program 172
of OS 171 of LPAR1 170 may be executing on threads 111 and 113 in
core1 110 and in threads 121 and 124 of core2 120. Subject to the
control of an OS, different programs may be dispatched on the same
or different threads, subject to dispatching rules and
quality-of-service agreements.
Also residing in the system memory 160 are various levels of
firmware, including for example, Millicode 162 and LPAR hypervisor
163. The Millicode 162 can be embodied as firmware to support
lower-level system functions. The LPAR hypervisor 163 may be, for
example, licensed internal code such as the IBM
Processor-Resource/System Manager.TM. (PR/SM.TM.). The LPAR
hypervisor 163 can establish the LPARs 170, 180, 190 and may manage
dispatching on the cores 102. When the MT facility 103 is installed
in the computer system 100, the Millicode 162 and LPAR hypervisor
163 also contain MT facility support code 164 and 165 respectively.
The MT facility support code 164 and 165 may be considered part of
the MT facility 103, as logic to support MT can be distributed
between the Millicode 162, LPAR hypervisor 163, and the cores 102.
Although not depicted, each of the OSs 171, 181, 191 can also
include MT facility support code to enable and exploit MT in their
respective LPARs 170, 180, 190.
FIG. 1B shows the same computing system 100 as FIG. 1A, except that
in the computing environment of FIG. 1B, core4 140 is now assigned
to LPAR3 190 instead of LPAR2 180. Also note that unlike FIG. 1A,
where threads 143 and 144 were not operational, in FIG. 1B, all
four threads 141-144 are operational when LPAR3 190 is dispatched
on core4 140. The dispatching and undispatching of an LPAR on a
core 102 is dynamic, and at other times other LPARs (not shown) may
be operating on the same cores 102.
Turning now to FIG. 2, a block diagram of processing circuitry 200
for implementing a processing core, such as one of the cores 102 in
FIGS. 1A and 1B, is generally shown in accordance with an
embodiment. The processing circuitry 200 is an example of a
processing circuit that can support one or more threads
simultaneously in a MT environment. The processing circuitry 200
shown in FIG. 2 includes a system controller interface unit 202
that can couple the processing circuitry 200 to other processors
and peripheral devices. The system controller interface unit 202
can also connect a Dcache 204, which reads and stores data values,
an Icache 208, which reads program instructions, and a cache
interface unit 206 to external memory, processors, and other
peripheral devices.
The Icache 208 can provide loading of instruction streams in
conjunction with an instruction fetch unit (IFU) 210, which
pre-fetches instructions and may include speculative loading and
branch prediction capabilities. The fetched instructions can be
provided to an instruction decode unit (IDU) 212 for decoding into
instruction processing data.
The IDU 212 can provide the instructions to an issue unit 214 which
can control the issuing of the instructions to various execution
units, such as one or more fixed point units (FXU) 216 for
executing general operations and one or more floating point units
(FPU) 218 for executing floating point operations. The FPUs 218 can
include a binary floating point unit (BFU) 220, a decimal floating
point unit (DFU) 222, or any other floating point unit. The issue
unit 214 can also be coupled to one or more load/store units (LSU)
228 via one or more LSU pipelines. The multiple LSU pipelines are
treated as execution units for performing loads and stores and
address generation for branches. Both the LSU 228 and the IFU 210
can utilize a translation-lookaside-buffer (TLB) 230 to provide
buffered translations for the operand and instruction
addresses.
The FXU 216 and FPU 218 are coupled to various resources such as
general-purpose registers (GPR) 224 and floating point registers
(FPR) 226. The GPR 224 and FPR 226 provide data value storage for
data values loaded and stored from the Dcache 204 by a LSU 228.
The processing circuitry 200 can also include counters and/or
timers 250 to support system time-base generation and diagnostic
actions. For example, the counters and/or timers 250 may be used to
support time-of-day, as well as various diagnostic and measurement
facilities.
Turning now to FIG. 3, a computing environment similar to FIG. 1A
is depicted except that in FIG. 3, a second-level hypervisor 300 is
executing in LPAR2 180 of the computer system 100. The second-level
hypervisor 300, for example, the IBM z/VM operating system,
includes MT support code 301, similar to the MT support code 165
provided by the LPAR (first-level) hypervisor 163. The second-level
hypervisor 300 provides support for a plurality of virtual machines
310, 320, and 330 (also referred to as configurations) in which
guest operating systems 311, 321, and 331 operate respectively. The
guest operating systems 311, 321, and 331 may include, for example,
Linux or the IBM z/OS, z/VM, or z/TPF OS, or may include a guest
development environment such as the IBM conversational monitor
system (CMS). Each guest OS 311, 321, and 331 may or may not enable
multithreading, in which case the second-level hypervisor 300 may
be responsible for dispatching the guest OSs 311, 321, 331 and
associated programs 312, 313, 322, 323, 332, and 333 using the
physical processing resources (cores 130, 140 and threads 131-134,
141-144) that are available to the LPAR2 180 in which the
second-level hypervisor 300 operates. The programs 312, 313, 322,
323, 332, 333 of the various virtual machines 310, 320, 330 can
execute on the threads 131-134, 141-144 available to the respective
guest OSs 311, 321, and 331. The guest OSs 311, 321, and 331 need
not include MT support code, as they can benefit from MT
transparently.
Turning now to FIG. 4, an example of hypervisor context retention
in a computing environment that may be implemented in accordance
with an embodiment is depicted. In the example of FIG. 4, a number
of support structures are depicted within the LPAR hypervisor 163
of FIGS. 1A and 1B. For example, structures 410 can support LPAR1
170 of FIG. 1A, including state descriptions and satellite blocks
that store architected register context (i.e., thread context) for
logical threads 411, 412, 413, 414, 421, 422, 423, 424 which are
currently running on physical threads 111, 112, 113, 114, 121, 122,
123, 124 as shown in FIG. 1A. While these logical threads are
dispatched, the physical threads hold the current architected
register context of the threads. The architected register context
will be maintained in the state descriptions and satellite blocks
when they are no longer dispatched. Structures 430 can support
LPAR2 180 of FIG. 1A, including state descriptions and satellite
blocks that store architected register context for logical threads
431, 432, 441, 442 which are currently running on physical threads
131, 132, 141, 142 as shown in FIG. 1A. Structures 450 can support
LPAR3 190 of FIG. 1A, including state descriptions and satellite
blocks that store architected register context for logical threads
451 which is currently running on physical thread 151 as shown in
FIG. 1A. Structures 450 also include state descriptions and
satellite blocks that store architected register context for
logical threads 461, 462, 463 and 464 which are not currently
dispatched on a physical processor (as shown with shading). Other
structures supporting LPARs that are not dispatched on physical
cores can also be retained by the LPAR hypervisor 163, such as
structures 470 for an LPAR A (not depicted in FIG. 1A) including
state descriptions and satellite structures for logical threads
471, 472, 473, and 474. Further structure examples include
structures 480 supporting non-dispatched LPAR B (not depicted in
FIG. 1A) including state descriptions and satellite structures for
logical threads 481 and 482, as well as structures 484 for
non-dispatched LPAR C (not depicted in FIG. 1A) for logical thread
485.
Although a number of structures are depicted in the example of FIG.
4, it will be understood that additional structures can be
supported by the LPAR hypervisor 163 and elsewhere in computer
system 100 to manage multithreading. For example, structures to
support multithreading of virtual machines 310, 320, 330 of FIG. 3
can be retained by the second-level hypervisor 300 of FIG. 3.
Turning now to FIG. 5, a process flow 500 for dynamic enablement of
multithreading is depicted in accordance with an embodiment. At
block 502, a primary thread executes in a single thread (ST) mode.
At block 504, a multithreading (MT) mode setting instruction is
fetched in the ST mode. In executing this instruction as depicted
collectively at 505, a number of threads requested from a location
specified by the MT mode setting instruction is obtained at block
506. The location can be specified by a parameter register when
issuing the set-MT mode instruction. The MT mode setting
instruction can be a signal processor (SIGP) instruction including
a set-MT order and a program-specified maximum thread-id (PSMTID)
associated with the number of threads requested. An example of a
process associated with a set-MT order of a SIGP instruction is
further described herein in reference to FIG. 7.
Continuing with process 500, at block 508, a determination is
performed as to whether the number of threads requested indicates
multiple threads. For example, multiple threads can be indicated by
a value greater than one. In embodiments where a value of zero
indicates a single thread, a value of one or more than one can
indicate multiple threads. Based on determining that the number of
threads requested does not indicate multiple threads, the core
remains in ST mode at block 510, the execution of the set-MT mode
instruction is complete, and control returns to block 502. Based on
determining that the number of threads requested indicates multiple
threads, MT mode is enabled at block 512, and the execution of the
set-MT mode instruction is complete. At block 514, multiple threads
are executed including the primary and one or more secondary
threads. At block 516, if there is no reset or deactivation, the
process 500 loops back to block 514; otherwise, at block 518, MT
mode is disabled based on a reset or a deactivation of the
configuration which reverts to ST mode. As part of disabling the MT
mode, the number of threads (PSMTID) is retained for a non-clearing
reset or zeroed for a clearing reset. The process 500 returns to
block 502.
A CPU can enter a load state when a load-normal, load-with-dump,
load-clear, or load-clear-list-directed key is activated. If a
channel-command word (CCW)-type initial-program-loading operation
is completed successfully, the CPU changes from the load state to
the operating state.
A CPU reset can be used to clear equipment-check indications and
any resultant unpredictability in the CPU state with the least
amount of information destroyed. In particular, it can be used to
clear check conditions when the CPU state is to be preserved for
analysis or resumption of the operation. If a CPU reset is caused
by the activation of the load-normal or load-with-dump key, (a) it
can set an architectural mode to a default mode, and (b) if the
multithreading facility is installed and enabled, multithreading is
disabled. When the CPU reset sets the default mode, it can save the
current PSW so that PSW can be restored.
An initial CPU reset provides functions of a CPU reset together
with initialization of the current PSW, CPU timer, clock
comparator, and other registers, such as: breaking-event-address,
captured-PSW, control, floating-point-control, prefix, and TOD
programmable registers. The initial CPU reset can set the
architectural mode to the default mode if it is caused by
activation of the load-normal or load-with-dump key. If
multithreading is enabled when an initial CPU reset is caused by
activation of the load-normal or load-with-dump key, the
initial-CPU-reset functions can be performed for the
lowest-numbered CPU of a core, and the CPU reset is performed for
all other CPUs in the core. A clearing reset causes the initial CPU
reset and subsystem reset to be performed and, additionally, clears
or initializes all storage locations and registers in all CPUs in
the configuration, with the exception of the TOD clock. Clearing
does not affect external storage, such as direct-access storage
devices used by the control program to hold the contents of
unaddressable pages.
A CPU power-on reset causes the initial CPU reset to be performed
and clears the contents of general registers, access registers,
control registers, and floating-point registers to zeroes/default
values with a valid checking-block code. It will be understood that
clearing or initializing of states need not be to zero values but
can default to non-zero values in the cleared state. If a CPU
power-on reset establishes the configuration, it can set the
architectural mode to the default mode; otherwise, it may set the
architectural mode to that of the CPUs already in the
configuration. CPU reset, initial CPU reset, subsystem reset, and
clear reset may be initiated manually.
In exemplary embodiments, each CPU has a number assigned, called
its CPU address. A CPU address uniquely identifies one CPU within a
configuration. A CPU is designated by specifying this address in a
CPU-address field of a SIGP instruction. A CPU signaling a
malfunction alert, emergency signal, or external call can be
identified by storing this address in the CPU-address field with
the interruption. The CPU address is assigned by a
configuration-definition process and is not typically changed as a
result of reconfiguration changes. A program can determine the
address of a CPU by using a store CPU address instruction. The
store CPU address instruction can also be used to identify a CPU
address by which a CPU is identified in a multiprocessing
configuration.
When multithreading is enabled, the CPU address can include a core
identification (core ID), concatenated with an identification of a
CPU within the core. The CPU identification within a core is a
thread identification (thread ID, or TID). Within a configuration,
all cores provide the same number of CPUs; however, depending on
the model and CPU type, some CPUs in a core may not be
operational.
Based on the PSMTID of a parameter register used by the signal
processor set multithreading order, a fixed number of bits
represent the thread identification. This number of bits is
referred to as the TID width.
The core ID can be formed from the rightmost bits of the CPU
address before multithreading is enabled. The core ID is shifted
left by TID-width bits, resulting in the leftmost bits of the CPU
address after multithreading is available. The thread ID has the
same TID-width number of bits, and occupies the rightmost bits of
the CPU address after multithreading is enabled. Thread IDs can be
assigned in a contiguous range of numbers. Table 1 illustrates an
example relationship of the PSMTID, the TID width and the
CPU-address bits comprising the core identification and thread
identification.
TABLE-US-00001 TABLE 1 Example address bit mapping CPU Address Bits
PSMTID TID Width Core ID Thread ID 0 0 0-15 -- 1 1 0-14 15 2-3 2
0-13 14-15 4-7 3 0-12 13-15 8-15 4 0-11 12-15 16-31 5 0-10
11-15
Address expansion is depicted in FIG. 6A as an example of a CPU
address expansion process 600A in accordance with an embodiment. At
block 602, a primary thread can be accessed in the ST mode using a
core address value 604 as a number of CPU address bits. Arrow 606
indicates switching from the ST mode to the MT mode. At block 608,
the primary thread or one or more secondary threads can be accessed
in the MT mode using an expanded address value 610. The expanded
address value 610 includes the core address value 604 shifted as a
shifted core address value 612 and concatenated with a thread
address value 614. The shifted core address value 612 is a core
identifier (core ID), and the thread address value 614 is a thread
identifier (TID). The shifted core address value 612 can be shifted
by an amount based on a requested maximum thread identifier, e.g.,
PSMTID. A number of TID bits in the thread address value 614 can be
determined based on the PSMTID as shown in table 1 above. The
thread address value 614 can be concatenated to low order bits of
the shifted core address value 612 to form the expanded address
value 610. A thread address value 614 of all zeroes would designate
the primary thread, and values greater than zero identify and
address secondary threads.
When switching between the MT mode and ST mode, either the core
address value 604 (ST mode) or the expanded address value 610 (MT
mode) is selected to use as a CPU address in a respective ST mode
or MT mode. The core address value 604 is an example of a
standard-format address used in ST mode, and the core reverts from
the MT mode to the ST mode based on disabling the MT mode. In an
exemplary embodiment, only the primary thread (i.e., not secondary
threads) is accessible based on disabling the MT mode. FIG. 6B
depicts an example of a CPU address contraction process 600B in
accordance with an embodiment. Arrow 616 of FIG. 6B illustrates
switching from the MT mode of block 608 back to the ST mode of
block 602. Reversion from the MT mode to the ST mode can include
shifting the expanded address value 610 to the right and
eliminating the thread address value 614 to form a standard-format
address including the core address value 604 (core ID) as the CPU
address from the shifted core address value 612.
When a reset function disables multithreading, (a) the CPU
address(es) of the CPU(s) having the thread-ID zero are shifted to
the right by the same TID-width number of bits used during
enablement, (b) zeroes are inserted in the TID-width number of bits
on the left of the address, and (c) the CPU address reverts to its
original non-multithreading format (i.e., standard-format address).
All CPUs in a core having nonzero thread IDs when multithreading is
enabled are no longer operational when multithreading is
disabled.
When multithreading is not enabled, the CPU address remains
unchanged from the value assigned by the configuration-definition
process. In this case, the thread identification does not
exist.
A number of signal processor orders can provide orders to CPUs
including, for example, start, stop, restart, stop and store
status, initial CPU reset, CPU reset, store status at address, set
architecture, sense running status, set multithreading, store
additional status at address, and the like. An initial CPU reset or
a CPU reset can be initiated by a signal processor instruction and
does not affect the architectural mode or other CPUs, does not
disable multithreading, and does not cause I/O to be reset.
A set architecture order specifies an architectural mode to which
all CPUs in the configuration are to be set. Architecture
differences can include different addressing modes, register
definitions, and instructions supported by the CPUs. Upon a change
in architectural mode, select bit fields of registers can be set to
a default state (e.g., zeroed), access-register-translation
lookaside buffers (ALBs) and translation lookaside buffers (TLBs)
of all CPUs in the configuration are cleared, and a serialization
and checkpoint-synchronization function can be performed on all
CPUs in the configuration.
A sense running status order can indicate whether an addressed CPU
is running. In ST mode, an indicator can be returned as a
running/not running status. In MT mode, an indicator can be used to
identify whether any CPU of the core in which the addressed CPU is
a member is running, or all CPUs of the core in which the addressed
CPU is a member are not running.
A set-MT order enables the multithreading facility. Bit positions
of a parameter register can contain the PSMTID to be provided in
the configuration. The PSMTID can be defined as one less than the
number of CPUs to be made addressable in each core. For example, a
value of 3 in designated bit positions indicates that a maximum of
four threads are to be provided. The contents of a CPU-address
register of the SIGP instruction can be ignored as all CPUs in the
configuration are considered to be addressed. If accepted, the
set-MT order is completed by all CPUs during the execution of the
SIGP instruction. With reference to FIG. 7, a process 700 for a
SIGP set-MT order 702 is depicted. An error indication can be
provided and enablement of the MT mode prevented based on
determining that the SIGP set-MT order 702 was issued with one or
more of: an invalid order, an incorrect state, and an invalid
parameter, as further described herein in reference to the process
700 of FIG. 7.
If the multithreading facility is not installed at block 704 or the
CPU is not enabled in a valid architecture mode 708, then the
set-MT order is not accepted and an invalid order indication may be
returned at blocks 706 or 710 respectively. If the other CPUs in
the configuration are not in the stopped or check-stop state at
block 712, or if the configuration is already enabled for
multithreading at block 716, the set-MT order is not accepted and
an incorrect state indication may be returned at block 714 or 718
respectively.
If the PSMTID is invalid at block 720, then the set-MT order is not
accepted and an invalid parameter indication may be returned at
block 722. When the PSMTID is zero at block 724, the configuration
is not enabled for multithreading, remains in ST mode, and provides
any status as a condition code at block 728. In an exemplary
embodiment, when the PSMTID is valid and nonzero, at block 726, the
configuration is enabled for multithreading, resulting in
CPU-address expansion, the ALBs and TLBs of all CPUs in the
configuration are cleared of their contents, and a serialization
and checkpoint-synchronization function is performed on all CPUs in
the configuration. Status can be provided at block 728 in a
condition code. Upon successful completion, all CPUs other than the
CPU executing the set-MT order remain in the stopped or check-stop
state. However, if a CPU was in the check-stop state before
multithreading is enabled, it may be unpredictable whether the CPUs
having nonzero thread IDs in the same core are placed in the
stopped or check-stopped state.
A thread context may also be referred to as an architected register
context. The architected register context (that is, the contents of
the PSW, CPU timer, clock comparator, general registers,
floating-point registers and floating-point control register,
vector registers, control registers, access registers, prefix
register, and TOD-programmable register, etc.) of each CPU before
multithreading is enabled becomes the architected register context
of the CPU having TID zero of each respective core after
multithreading is enabled. Similarly, the architected register
context of the CPU having TID zero of each core of an MT-enabled
configuration becomes the architected register context of each
respective CPU when multithreading is disabled as a result of the
activation of a load-normal or load-with-dump key.
The architected register context of all CPUs having a nonzero
thread identification can be retained when the multithreading
facility is disabled as a result of the activation of a load-normal
or load-with-dump key operation. If the multithreading facility is
subsequently re-enabled without an intervening clear reset, the
architected register context of all CPUs having a nonzero thread
identification are restored.
When multithreading is re-enabled after having been disabled by the
activation of the load-normal or load-with-dump key, if the value
of the PSMTID in bits of the parameter register differs from that
used in the preceding enablement, then the architected register
context of all CPUs having nonzero thread IDs can be
unpredictable.
A store system information instruction can be used to store
information about a component or components of a configuration into
a system-information block (SYSIB). The SYSIB can include an MT
installed field, an MT general field, a total CPU/core count, a
configured CPU/core count, a standby CPU/core count, a reserved
CPU/core count, and other fields. The MT installed field can
indicate whether the multithreading facility is installed and may
also indicate the highest supported TID for a first core type,
e.g., a specialty core type. The MT general field can indicate the
highest supported TID for a second core type, e.g., a general core
type. The highest supported TID in the MT general field may be
limited to being less than or equal to the highest supported TID in
the MT installed field. The total CPU/core count may indicate a
total number of general CPUs or cores comprising general CPUs in
the configuration, whether in the configured, standby, or reserved
state. The configured CPU/core count can indicate a number of
general CPUs or cores comprising general CPUs in the configured
state, i.e., in the configuration and ready to execute programs.
The standby CPU/core count indicates a number of general CPUs or
cores comprising general CPUs in the standby state, i.e., not
available to be used to execute programs until placed in the
configured state. The reserved CPU/core count indicates a number of
general CPUs or cores comprising general CPUs in the reserved
state, i.e., unavailable to be used to execute programs and unable
to be placed in the configured state.
Turning now to FIG. 8, a block diagram of processing circuitry 800
for implementing hardware counters to provide MT utilization
information in accordance with an embodiment is generally shown. In
an embodiment, the processing circuitry 800 shown in FIG. 8 is
included in the processing circuitry 200 shown in FIG. 2. The
processing circuitry 800 includes execution event counters 802, a
core clock 806, a control signal 804, a PSW 810, and a thread
validity mask (TVM) 808. In an embodiment where a physical core
includes four threads, a first set of counters 802 is assigned to
count execution events and clock cycles when one thread is active,
a second set of counters 802 is assigned to count execution events
and clock cycles when two threads are active, a third set of
counters 802 are assigned to count execution events and clock
cycles when three threads are active, and a fourth set of counters
802 are assigned to count execution events and clock cycles when
four threads are active.
A thread is active when it is valid and is not currently in a wait
state (e.g., waiting for an interrupt and/or not fetching
instructions). Thus, an active thread can be fetching instructions.
The validity of a thread can be determined, for example, based on
contents of the thread validity mask (TVM) 808, which can be
provided as part of the state information about the logical threads
currently executing on the core. In an embodiment, the TVM 808
includes a bit for each thread which indicates whether a particular
thread is valid or invalid, and can be cached in hardware on the
core 110. The validity of a thread can also be determined based on
one or more signals containing thread validity information that are
received from system management software (e.g., a hypervisor,
BIOS).
In an embodiment, a PSW 810 for a thread can be used to determine
whether a thread is currently in a wait state. Generally, an
interrupt will cause a thread in a wait state to become active.
Alternatively, in another embodiment, other internal processor
state information may be used to determine when a thread is active.
The core clock 806 shown in FIG. 2, which is used by the counters
802 to count clock cycles, can be implemented by, or derived from,
a system clock used by the processing circuitry 200. Also shown in
FIG. 8 is a control signal 804 which may be used to determine when
instructions have completed. Alternatively, information from an
issue unit (e.g., issue unit 214 in FIG. 2) or an instruction fetch
unit (e.g., instruction fetch unit 210 in FIG. 2) can be used to
indicate to the counters 802 a number of instructions
completed.
FIG. 9 depicts an example of a configuration that captures
utilization counters in accordance with an embodiment. In the
example of FIG. 9, a configuration 950 includes a pair of cores
900A and 900B. Each of the cores 900A and 900B includes utilization
counters 902 and four threads, thread0, thread1, thread2, and
thread3. In addition, the utilization counters 902 can be divided
into different sets of counters for each possible active thread
count (in this case 1, 2, 3, 4). The utilization counters 902 shown
in FIG. 9 include: set one--MT1CC for counting a number of clock
cycles when one of the four threads is active and MT1IC for
counting a number of instructions that were completed when one of
the four threads is active; set two--MT2CC for counting a number of
clock cycles when two of the four threads are active and MT2IC for
counting a number of instructions that were completed when two of
the four threads are active; set 3--MT3CC for counting a number of
clock cycles when three of the four threads are active and MT3IC
for counting a number of instructions that were completed when
three of the four threads are active; and set 4--MT4CC for counting
a number of clock cycles when all of the four threads are active
and MT4IC for counting a number of instructions that were completed
when all of the four threads are active.
In an embodiment, the utilization counters 902 are activated on
core 900A when MT is enabled on the core 900A via, for example upon
completion of an accepted set-multithreading signal processor
(SIGP) order. Similarly, the utilization counters 902 can be
activated on core 900B when MT is enabled on core 900B. In an
embodiment, the utilization counters 902 are disabled on core 900A
by any action which causes the MT to be disabled on the core 900A.
Similarly, the utilization counters 902 can be disabled on core
900B when MT is disabled on core 900B. In embodiment, after MT is
disabled on a core the counter set of MT1CC and MT1IC can continue
to increment when the core is operating in ST mode.
In an embodiment, the contents of the utilization counters can be
read by a software instruction executed, for example by an
operating system or hypervisor.
Turning now to FIG. 10, a process flow for MT utilization counting
on a core is generally shown in accordance with an embodiment.
Utilization counters for a core are activated at block 1002. The
activating of the utilization counters can include resetting the
counters. In an embodiment, the processing shown in FIG. 10, from
block 1004 through block 1026, is performed once per clock cycle.
The processing shown in FIG. 10 can be used to increment one or
more utilization counters based on an aggregation of one or more
execution events at the multiple threads of the core.
At block 1004 it is determined (e.g., based on contents of a TVM
and/or PSW) whether exactly one thread is active. If one thread is
active, then processing continues at block 1006 where the MT1CC
counter, which counts the number of clock cycles where the core has
one thread active, is incremented by one. At block 1008 it is
determined (e.g., based on the value of a control signal) if an
execution event(s) has been detected. If an execution event(s) has
been detected, then block 1010 is performed to increment the
corresponding counter, which counts the number of execution
event(s) completed by the core when one thread is active.
Processing then continues at block 1004 in the next clock cycle. If
an execution event was not detected, as determined at block 1008,
processing continues at block 1004 in the next clock cycle.
If it is determined at block 1004, that more than one thread is
active (implied since exactly one thread is not active), then the
process continues at block 1012, where it is it is determined
whether exactly two threads are active. If two threads are active,
then processing continues at block 1014 where the MT2CC counter,
which counts the number of clock cycles where the core has two
threads active, is incremented by one. At block 1016 it is
determined if an execution event(s) has been detected. If an
execution event(s) has been detected on either of the two threads,
then block 1018 is performed to increment the corresponding
counter, which counts the number of execution event(s) completed by
the core when two threads are active. In an embodiment, if an
execution event is detected on both threads, then the corresponding
counter is incremented by two. Processing then continues at block
1004 in the next clock cycle. If an execution event was not
detected, as determined at block 1016, processing continues at
block 1004 in the next clock cycle.
Similar processing continues for each thread in the core. At block
1020, if it is determined that exactly "N" threads are active, then
processing continues at block 1022, otherwise an error condition
can be reported. At block 1022, the MTNCC counter, which counts the
number of clock cycles where the core has N threads active, is
incremented by one. At block 1024 it is determined if an execution
event(s) has been detected. If an execution event(s) has been
detected on any of the N threads, then block 1026 is performed to
increment the corresponding counter, which counts the number of
execution events detected by the core when N threads are active.
Processing then continues at block 1004 in the next clock cycle. If
an execution event was not detected, as determined at block 1024,
processing continues at block 1004 in the next clock cycle.
In this manner, the occurrence of an execution event is tracked and
the results aggregated across multiple cores. An execution event,
as used herein, refers to any event on a thread of the core that
can be tracked such as, but not limited to a clock cycle, an
instruction completion, a cache miss, and a branch
misprediction.
Technical effects and benefits include the ability to collect
utilization information for a core in a computer system that
supports both a single thread mode and a multithreading mode of
operation.
Embodiments include a method, system, and computer program product
for tracking utilization in a multithreading (MT) computer system.
According to one aspect, a computer system includes a configuration
with a core configured to operate in a MT mode that supports
multiple threads on shared resources of the core. The core is
configured to perform a method that includes resetting a plurality
of utilization counters. The utilization counters include a
plurality of sets of counters. During each clock cycle on the core,
a set of counters is selected from the plurality of sets of
counters. The selecting is based on a number of currently active
threads on the core. In addition, during each clock cycle a counter
in the selected set of counters is incremented based on an
aggregation of one or more execution events at the multiple threads
of the core. Values of the utilization counters are provided to a
software program.
According to another aspect, a computer implemented method for
tracking utilization in a configuration is provided. The
configuration includes a core configured to operate in a
multithreading (MT) mode. The MT mode supports multiple threads on
shared resources of the core. The method includes resetting a
plurality of utilization counters. The utilization counters include
a plurality of sets of counters. During each clock cycle on the
core, a set of counters is selected from the plurality of sets of
counters. The selecting is based on a number of currently active
threads on the core. In addition, during each clock cycle a counter
in the selected set of counters is incremented based on an
aggregation of one or more execution events at the multiple threads
of the core. Values of the utilization counters are provided to a
software program.
A further aspect is a computer program product for tracking
utilization in a configuration. The configuration includes a core
configured to operate in a multithreading (MT) mode. The MT mode
supports multiple threads on shared resources of the core. The
computer program product includes a computer readable storage
medium having program instructions embodied therewith, wherein the
computer readable storage medium is not a signal, the program
instructions readable by a processing circuit to cause the
processing circuit to perform a method. The method includes
resetting a plurality of utilization counters. The utilization
counters include a plurality of sets of counters. During each clock
cycle on the core, a set of counters is selected from the plurality
of sets of counters. The selecting is based on a number of
currently active threads on the core. In addition, during each
clock cycle a counter in the selected set of counters is
incremented based on an aggregation of one or more execution events
at the multiple threads of the core. Values of the utilization
counters are provided to a software program.
In addition to one or more of the features described above, or as
an alternative, further embodiments can include where the execution
event includes a clock cycle and the counter in the selected set of
counters is incremented by one.
In addition to one or more of the features described above, or as
an alternative, further embodiments can include where the execution
event further includes an instruction completion and an other
counter in the selected set of counters is incremented based on a
number of instruction completions on all of the currently active
threads during the clock cycle.
In addition to one or more of the features described above, or as
an alternative, further embodiments can include where the execution
event further includes a cache miss and an other counter in the
selected set of counters is incremented based on a number of cache
misses on all of the currently active threads during the clock
cycle.
In addition to one or more of the features described above, or as
an alternative, further embodiments can include where the execution
event further includes a branch misprediction and an other counter
in the selected set of counters is incremented based on a number of
branch mispredictions on all of the currently active threads during
the clock cycle.
In addition to one or more of the features described above, or as
an alternative, further embodiments can include where a thread is
currently active when the thread is valid and not in a wait
state.
In addition to one or more of the features described above, or as
an alternative, further embodiments can include where the software
program is an operating system or a hypervisor.
The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the invention. As used herein, the singular forms "a", "an" and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises" and/or "comprising," when used in this
specification, specify the presence of stated features, integers,
steps, operations, elements, and/or components, but do not preclude
the presence or addition of one or more other features, integers,
steps, operations, element components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of
all means or step plus function elements in the claims below are
intended to include any structure, material, or act for performing
the function in combination with other claimed elements as
specifically claimed. The description of the present invention has
been presented for purposes of illustration and description, but is
not intended to be exhaustive or limited to the invention in the
form disclosed. Many modifications and variations will be apparent
to those of ordinary skill in the art without departing from the
scope and spirit of the invention. The embodiment was chosen and
described in order to best explain the principles of the invention
and the practical application, and to enable others of ordinary
skill in the art to understand the invention for various
embodiments with various modifications as are suited to the
particular use contemplated.
The descriptions of the various embodiments of the present
invention have been presented for purposes of illustration, but are
not intended to be exhaustive or limited to the embodiments
disclosed. Many modifications and variations will be apparent to
those of ordinary skill in the art without departing from the scope
and spirit of the described embodiments. The terminology used
herein was chosen to best explain the principles of the
embodiments, the practical application or technical improvement
over technologies found in the marketplace, or to enable others of
ordinary skill in the art to understand the embodiments disclosed
herein.
Referring now to FIG. 11, a computer program product 1100 in
accordance with an embodiment that includes a computer readable
storage medium 1102 and program instructions 1104 is generally
shown.
The present invention may be a system, a method, and/or a computer
program product. The computer program product may include a
computer readable storage medium (or media) having computer
readable program instructions thereon for causing a processor to
carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that
can retain and store instructions for use by an instruction
execution device. The computer readable storage medium may be, for
example, but is not limited to, an electronic storage device, a
magnetic storage device, an optical storage device, an
electromagnetic storage device, a semiconductor storage device, or
any suitable combination of the foregoing. A non-exhaustive list of
more specific examples of the computer readable storage medium
includes the following: a portable computer diskette, a hard disk,
a random access memory (RAM), a read-only memory (ROM), an erasable
programmable read-only memory (EPROM or Flash memory), a static
random access memory (SRAM), a portable compact disc read-only
memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a
floppy disk, a mechanically encoded device such as punch-cards or
raised structures in a groove having instructions recorded thereon,
and any suitable combination of the foregoing. A computer readable
storage medium, as used herein, is not to be construed as being
transitory signals per se, such as radio waves or other freely
propagating electromagnetic waves, electromagnetic waves
propagating through a waveguide or other transmission media (e.g.,
light pulses passing through a fiber-optic cable), or electrical
signals transmitted through a wire.
Computer readable program instructions described herein can be
downloaded to respective computing/processing devices from a
computer readable storage medium or to an external computer or
external storage device via a network, for example, the Internet, a
local area network, a wide area network and/or a wireless network.
The network may comprise copper transmission cables, optical
transmission fibers, wireless transmission, routers, firewalls,
switches, gateway computers and/or edge servers. A network adapter
card or network interface in each computing/processing device
receives computer readable program instructions from the network
and forwards the computer readable program instructions for storage
in a computer readable storage medium within the respective
computing/processing device.
Computer readable program instructions for carrying out operations
of the present invention may be assembler instructions,
instruction-set-architecture (ISA) instructions, machine
instructions, machine dependent instructions, microcode, firmware
instructions, state-setting data, or either source code or object
code written in any combination of one or more programming
languages, including an object oriented programming language such
as Smalltalk, C++ or the like, and conventional procedural
programming languages, such as the "C" programming language or
similar programming languages. The computer readable program
instructions may execute entirely on the user's computer, partly on
the user's computer, as a stand-alone software package, partly on
the user's computer and partly on a remote computer or entirely on
the remote computer or server. In the latter scenario, the remote
computer may be connected to the user's computer through any type
of network, including a local area network (LAN) or a wide area
network (WAN), or the connection may be made to an external
computer (for example, through the Internet using an Internet
Service Provider). In some embodiments, electronic circuitry
including, for example, programmable logic circuitry,
field-programmable gate arrays (FPGA), or programmable logic arrays
(PLA) may execute the computer readable program instructions by
utilizing state information of the computer readable program
instructions to personalize the electronic circuitry, in order to
perform aspects of the present invention
Aspects of the present invention are described herein with
reference to flowchart illustrations and/or block diagrams of
methods, apparatus (systems), and computer program products
according to embodiments of the invention. It will be understood
that each block of the flowchart illustrations and/or block
diagrams, and combinations of blocks in the flowchart illustrations
and/or block diagrams, can be implemented by computer readable
program instructions.
These computer readable program instructions may be provided to a
processor of a general purpose computer, special purpose computer,
or other programmable data processing apparatus to produce a
machine, such that the instructions, which execute via the
processor of the computer or other programmable data processing
apparatus, create means for implementing the functions/acts
specified in the flowchart and/or block diagram block or blocks.
These computer readable program instructions may also be stored in
a computer readable storage medium that can direct a computer, a
programmable data processing apparatus, and/or other devices to
function in a particular manner, such that the computer readable
storage medium having instructions stored therein comprises an
article of manufacture including instructions which implement
aspects of the function/act specified in the flowchart and/or block
diagram block or blocks.
The computer readable program instructions may also be loaded onto
a computer, other programmable data processing apparatus, or other
device to cause a series of operational steps to be performed on
the computer, other programmable apparatus or other device to
produce a computer implemented process, such that the instructions
which execute on the computer, other programmable apparatus, or
other device implement the functions/acts specified in the
flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the
architecture, functionality, and operation of possible
implementations of systems, methods, and computer program products
according to various embodiments of the present invention. In this
regard, each block in the flowchart or block diagrams may represent
a module, segment, or portion of instructions, which comprises one
or more executable instructions for implementing the specified
logical function(s). In some alternative implementations, the
functions noted in the block may occur out of the order noted in
the figures. For example, two blocks shown in succession may, in
fact, be executed substantially concurrently, or the blocks may
sometimes be executed in the reverse order, depending upon the
functionality involved. It will also be noted that each block of
the block diagrams and/or flowchart illustration, and combinations
of blocks in the block diagrams and/or flowchart illustration, can
be implemented by special purpose hardware-based systems that
perform the specified functions or acts or carry out combinations
of special purpose hardware and computer instructions.
* * * * *