U.S. patent number 10,062,424 [Application Number 15/652,143] was granted by the patent office on 2018-08-28 for electronic device.
This patent grant is currently assigned to SK hynix Inc.. The grantee listed for this patent is SK hynix Inc.. Invention is credited to Won-Joon Choi, Ku-Youl Jung, Guk-Cheon Kim, Jeong-Myeong Kim, Yang-Kon Kim, Jong-Koo Lim.
United States Patent |
10,062,424 |
Kim , et al. |
August 28, 2018 |
Electronic device
Abstract
This technology provides an electronic device. An electronic
device in accordance with an implementation of this document may
include a semiconductor memory, and the semiconductor memory may
include: an under layer including a plurality of material layers
having a different crystal structures; a first magnetic layer
formed over the under layer and having a variable magnetization
direction; a tunnel barrier layer formed over the first magnetic
layer; and a second magnetic layer formed over the tunnel barrier
layer and having a pinned magnetization direction.
Inventors: |
Kim; Yang-Kon (Icheon-si,
KR), Kim; Guk-Cheon (Icheon-si, KR), Kim;
Jeong-Myeong (Icheon-Si, KR), Lim; Jong-Koo
(Icheon-Si, KR), Jung; Ku-Youl (Icheon-Si,
KR), Choi; Won-Joon (Icheon-Si, KR) |
Applicant: |
Name |
City |
State |
Country |
Type |
SK hynix Inc. |
Icheon-Si |
N/A |
KR |
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Assignee: |
SK hynix Inc. (Icheon-si,
KR)
|
Family
ID: |
58778166 |
Appl.
No.: |
15/652,143 |
Filed: |
July 17, 2017 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20170316814 A1 |
Nov 2, 2017 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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15073394 |
Mar 17, 2016 |
9711202 |
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Foreign Application Priority Data
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Nov 30, 2015 [KR] |
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10-2015-0168318 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
43/02 (20130101); H01L 43/08 (20130101); G11C
11/1697 (20130101); G11C 11/161 (20130101); H01L
43/10 (20130101) |
Current International
Class: |
G11C
11/16 (20060101); H01L 43/10 (20060101); H01L
43/02 (20060101); H01L 43/08 (20060101) |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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10-2016-0073782 |
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Jun 2016 |
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KR |
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Primary Examiner: Bernstein; Allison P
Attorney, Agent or Firm: Perkins Coie LLP
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATION
This patent document is a continuation of, and claims priority and
benefits of, U.S. patent application Ser. No. 15/073,394, published
as US2017/0154662 A1, entitled "ELECTRONIC DEVICE," and filed on
Mar. 17, 2016, which further claims priority of Korean Patent
Application No. 10-2015-0168318, entitled "ELECTRONIC DEVICE" and
filed on Nov. 30, 2015. The contents of the before-mentioned patent
applications (including US2017/0154662 A1) are incorporated herein
by reference in their entirety as part of the disclosure of this
document.
Claims
What is claimed is:
1. An electronic device comprising a semiconductor memory, wherein
the semiconductor memory comprises: a variable resistance element
that includes a free magnetic layer having a variable magnetization
direction and exhibits different resistance values for different
magnetization directions in the free magnetic layer; and an under
layer formed in direct contact with the free magnetic layer of the
variable resistance element and including a plurality of material
layers having different crystal structures; wherein the under layer
comprises: a first material layer having an FCC (Face Centered
Cubic) crystal structure and a second material layer having a NaCl
crystal structure and a third material layer having a wurtzite
crystal structure.
2. The electronic device of claim 1, wherein the third material
layer further comprises a dusting layer interposed between the
first material layer and the second material layer.
3. The electronic device of claim 2, wherein the dusting layer is
formed to have a thickness in a range from about 0.5 .ANG. to about
2 .ANG..
4. The electronic device of claim 2, wherein the dusting layer
comprises aluminum nitride (AlN), silver iodide (AgI), zinc oxide
(ZnO), cadmium sulfate (CdS), cadmium selenide (CdSe), silicon
carbide (SiC), galium nitride (GaN) or boron nitride (BN).
5. The electronic device of claim 1, wherein the third material
layer further comprises a dusting layer interposed between the
second material layer and the free magnetic layer.
6. The electronic device of claim 5, wherein the dusting layer is
formed to have a thickness in a range from about 0.5 .ANG. to about
2 .ANG..
7. The electronic device of claim 1, wherein the first material
layer comprises metal nitride having the FCC crystal structure.
8. The electronic device of claim 1, wherein the first material
layer comprises zirconium nitride (ZrN), hafnium nitride (HfN),
titanium nitride (TiN) or molybdenum nitride (MoN).
9. The electronic device of claim 1, wherein the second material
layer comprises metal oxide having the NaCl crystal structure.
10. The electronic device of claim 1, wherein the second material
layer comprises magnesium oxide (MgO) or zirconium oxide (ZrO).
11. The electronic device of claim 1, wherein the free magnetic
layer is a different crystal structure from the under layer.
12. The electronic device according to claim 1, further comprising
a microprocessor which includes: a control unit configured to
receive a signal including a command from an outside of the
microprocessor, and performs extracting, decoding of the command,
or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a
result that the control unit decodes the command; and a memory unit
configured to store data for performing the operation, data
corresponding to a result of performing the operation, or an
address of data for which the operation is performed, wherein the
semiconductor memory is part of the memory unit in the
microprocessor.
13. The electronic device according to claim 1, further comprising
a processor which includes: a core unit configured to perform,
based on a command inputted from an outside of the processor, an
operation corresponding to the command, by using data; a cache
memory unit configured to store data for performing the operation,
data corresponding to a result of performing the operation, or an
address of data for which the operation is performed; and a bus
interface connected between the core unit and the cache memory
unit, and configured to transmit data between the core unit and the
cache memory unit, wherein the semiconductor memory is part of the
cache memory unit in the processor.
14. The electronic device according to claim 1, further comprising
a processing system which includes: a processor configured to
decode a command received by the processor and control an operation
for information based on a result of decoding the command; an
auxiliary memory device configured to store a program for decoding
the command and the information; a main memory device configured to
call and store the program and the information from the auxiliary
memory device such that the processor can perform the operation
using the program and the information when executing the program;
and an interface device configured to perform communication between
at least one of the processor, the auxiliary memory device and the
main memory device and the outside, wherein the semiconductor
memory is part of the auxiliary memory device or the main memory
device in the processing system.
15. The electronic device according to claim 1, further comprising
a data storage system which includes: a storage device configured
to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and
from the storage device according to a command inputted form an
outside; a temporary storage device configured to temporarily store
data exchanged between the storage device and the outside; and an
interface configured to perform communication between at least one
of the storage device, the controller and the temporary storage
device and the outside, wherein the semiconductor memory is part of
the storage device or the temporary storage device in the data
storage system.
16. The electronic device according to claim 1, further comprising
a memory system which includes: a memory configured to store data
and conserve stored data regardless of power supply; a memory
controller configured to control input and output of data to and
from the memory according to a command inputted form an outside; a
buffer memory configured to buffer data exchanged between the
memory and the outside; and an interface configured to perform
communication between at least one of the memory, the memory
controller and the buffer memory and the outside, wherein the
semiconductor memory is part of the memory or the buffer memory in
the memory system.
17. The electronic device according to claim 1, wherein the
variable resistance element further includes a fixed magnetic layer
having a fixed magnetization direction and a tunnel barrier layer
arranged between the free magnetic layer and the fixed magnetic
layer.
18. The electronic device according to claim 1, wherein the third
material layer includes aluminum nitride (AlN), silver iodide
(AgI), zinc oxide (ZnO), cadmium sulfate (CdS), cadmium selenide
(CdSe), silicon carbide (SiC), galium nitride (GaN) or boron
nitride (BN).
19. An electronic device comprising a semiconductor memory, wherein
the semiconductor memory comprises: a variable resistance element
that includes a free magnetic layer having a variable magnetization
direction and exhibits different resistance values for different
magnetization directions in the free magnetic layer; and an under
layer formed in direct contact with the free magnetic layer of the
variable resistance element and including a plurality of material
layers having different crystal structures; wherein the under layer
comprises: a first material layer having an FCC (Face Centered
Cubic) crystal structure and a second material layer having a NaCl
crystal structure, wherein the free magnetic layer has a BCC (Body
Centered Cubic) crystal structure.
20. The electronic device according to claim 19, wherein the under
layer further comprises a third material layer having a wurtzite
crystal structure.
Description
TECHNICAL FIELD
This patent document relates to memory circuits or devices and
their applications in electronic devices or systems.
BACKGROUND
Recently, as electronic devices or appliances trend toward
miniaturization, low power consumption, high performance,
multi-functionality, and so on, there is a demand for electronic
devices capable of storing information in various electronic
devices or appliances such as a computer, a portable communication
device, and so on, and research and development for such electronic
devices have been conducted. Examples of such electronic devices
include electronic devices which can store data using a
characteristic switched between different resistant states
according to an applied voltage or current, and can be implemented
in various configurations, for example, an RRAM (resistive random
access memory), a PRAM (phase change random access memory), an FRAM
(ferroelectric random access memory), an MRAM (magnetic random
access memory), an E-fuse, etc.
SUMMARY
The disclosed technology in this patent document includes memory
circuits or devices and their applications in electronic devices or
systems and various implementations of an electronic device, in
which an electronic device includes a semiconductor memory which
can improve characteristics of a variable resistance element.
In an implementation, an electronic device may include a
semiconductor memory, and the semiconductor memory may include an
under layer including a plurality of material layers having a
different crystal structures; a first magnetic layer formed over
the under layer and having a variable magnetization direction; a
tunnel barrier layer formed over the first magnetic layer; and a
second magnetic layer formed over the tunnel barrier layer and
having a pinned magnetization direction.
The under layer may include a first material layer; a second
material layer; and a third material layer which have different
crystal structures from each other, wherein the third material
layer may include a dusting layer. The under layer may have a
multi-stack structure in which the first material layer, the second
material layer and the third material layer are sequentially
stacked. The third material layer may be formed as thinly as
possible within a predetermined range. The under layer may have a
multi-stack structure in which the first material layer, the third
material layer and the second material layer are sequentially
stacked. The third material layer may be formed as thickly as
possible within a predetermined range. The under layer may include
a first material layer has an FCC (Face Centered Cubic) crystal
structure, a second material layer has a NaCl crystal structure,
and a third material layer has a wurtzite crystal structure. The
first material layer may include metal nitride having an FCC
crystal structure. The first material layer may include zirconium
nitride (ZrN), hafnium nitride (HfN), titanium nitride (TiN) or
molybdenum nitride (MoN). The second material layer may include
metal oxide having a NaCl crystal structure. The second material
layer may include magnesium oxide (MgO) or zirconium oxide (ZrO).
The third material layer may include aluminum nitride (AlN), silver
iodide (AgI), zinc oxide (ZnO), cadmium sulfate (CdS), cadmium
selenide (CdSe), silicon carbide (SiC), galium nitride (GaN) or
boron nitride (BN).
The electronic device may further comprising a microprocessor which
includes: a control unit configured to receive a signal including a
command from an outside of the microprocessor, and performs
extracting, decoding of the command, or controlling input or output
of a signal of the microprocessor; an operation unit configured to
perform an operation based on a result that the control unit
decodes the command; and a memory unit configured to store data for
performing the operation, data corresponding to a result of
performing the operation, or an address of data for which the
operation is performed, wherein the semiconductor memory is part of
the memory unit in the microprocessor.
The electronic device may further comprising a processor which
includes: a core unit configured to perform, based on a command
inputted from an outside of the processor, an operation
corresponding to the command, by using data; a cache memory unit
configured to store data for performing the operation, data
corresponding to a result of performing the operation, or an
address of data for which the operation is performed; and a bus
interface connected between the core unit and the cache memory
unit, and configured to transmit data between the core unit and the
cache memory unit, wherein the semiconductor memory is part of the
cache memory unit in the processor.
The electronic device may further comprising a processing system
which includes: a processor configured to decode a command received
by the processor and control an operation for information based on
a result of decoding the command; an auxiliary memory device
configured to store a program for decoding the command and the
information; a main memory device configured to call and store the
program and the information from the auxiliary memory device such
that the processor can perform the operation using the program and
the information when executing the program; and an interface device
configured to perform communication between at least one of the
processor, the auxiliary memory device and the main memory device
and the outside, wherein the semiconductor memory is part of the
auxiliary memory device or the main memory device in the processing
system.
The electronic device may further comprising a data storage system
which includes: a storage device configured to store data and
conserve stored data regardless of power supply; a controller
configured to control input and output of data to and from the
storage device according to a command inputted form an outside; a
temporary storage device configured to temporarily store data
exchanged between the storage device and the outside; and an
interface configured to perform communication between at least one
of the storage device, the controller and the temporary storage
device and the outside, wherein the semiconductor memory is part of
the storage device or the temporary storage device in the data
storage system.
The electronic device may further comprising a memory system which
includes: a memory configured to store data and conserve stored
data regardless of power supply; a memory controller configured to
control input and output of data to and from the memory according
to a command inputted form an outside; a buffer memory configured
to buffer data exchanged between the memory and the outside; and an
interface configured to perform communication between at least one
of the memory, the memory controller and the buffer memory and the
outside, wherein the semiconductor memory is part of the memory or
the buffer memory in the memory system.
In another implementation, an electronic device may include a
variable resistance element that includes a free magnetic layer
having a variable magnetization direction and exhibits different
resistance values for different magnetization directions in the
free magnetic layer; and an under layer formed in direct contact
with the free magnetic layer of the variable resistance element and
including a plurality of material layers having different crystal
structures. The under layer may include a first material layer
having an FCC (Face Centered Cubic) crystal structure and a second
material layer having a NaCl crystal structure.
Further, in the electronic device in accordance with the
implementation, the under layer may further include a dusting layer
interposed between the first material layer and the second material
layer and having a wurtzite crystal structure. The dusting layer
may be formed as thickly as possible within a predetermined
range.
Moreover, in the electronic device in accordance with the
implementation, the under layer may further include a dusting layer
interposed between the second material layer and the free magnetic
layer and having a wurtzite crystal structure. The dusting layer
may be formed as thinly as possible within a predetermined
range.
The dusting layer may include aluminum nitride (AlN), silver iodide
(AgI), zinc oxide (ZnO), cadmium sulfate (CdS), cadmium selenide
(CdSe), silicon carbide (SiC), galium nitride (GaN) or boron
nitride (BN). The first material layer may include metal nitride
having an FCC crystal structure. The first material layer may
include zirconium nitride (ZrN), hafnium nitride (HfN), titanium
nitride (TiN) or molybdenum nitride (MoN). The second material
layer may include metal oxide having a NaCl crystal structure. The
second material layer may include magnesium oxide (MgO) or
zirconium oxide (ZrO). The free magnetic layer may be a different
crystal structure from the under layer. The first magnetic layer
may have a BCC (Body Centered Cubic) crystal structure.
These and other aspects, implementations and associated advantages
are described in greater detail in the drawings, the description
and the claims.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view illustrating a variable resistance
element in accordance with a first implementation of the present
disclosure.
FIG. 2 is a cross-sectional view illustrating a variable resistance
element in accordance with a second implementation of the present
disclosure.
FIG. 3 is a graph illustrating a change in a magnetic anisotropy
field in the free layer depending on a thickness of the dusting
layer in the variable resistance element in accordance with the two
different implementations in FIGS. 1 and 2 of the present
disclosure.
FIG. 4 is a cross-sectional view illustrating a memory device and a
method for fabricating the same in accordance with an
implementation of the present disclosure.
FIG. 5 is a cross-sectional view illustrating a memory device and a
method for fabricating the same in accordance with another
implementation of the present disclosure.
FIG. 6 is an example of configuration diagram of a microprocessor
implementing memory circuitry based on the disclosed
technology.
FIG. 7 is an example of configuration diagram of a processor
implementing memory circuitry based on the disclosed
technology.
FIG. 8 is an example of configuration diagram of a system
implementing memory circuitry based on the disclosed
technology.
FIG. 9 is an example of configuration diagram of a data storage
system implementing memory circuitry based on the disclosed
technology.
FIG. 10 is an example of configuration diagram of a memory system
implementing memory circuitry based on the disclosed
technology.
DETAILED DESCRIPTION
Various examples and implementations of the disclosed technology
are described below in detail with reference to the accompanying
drawings.
The drawings may not be necessarily to scale and in some instances,
proportions of at least some of structures in the drawings may have
been exaggerated in order to clearly illustrate certain features of
the described examples or implementations. In presenting a specific
example in a drawing or description having two or more layers in a
multi-layer structure, the relative positioning relationship of
such layers or the sequence of arranging the layers as shown
reflects a particular implementation for the described or
illustrated example and a different relative positioning
relationship or sequence of arranging the layers may be possible.
In addition, a described or illustrated example of a multi-layer
structure may not reflect all layers present in that particular
multilayer structure (e.g., one or more additional layers may be
present between two illustrated layers). As a specific example,
when a first layer in a described or illustrated multi-layer
structure is referred to as being "on" or "over" a second layer or
"on" or "over" a substrate, the first layer may be directly formed
on the second layer or the substrate but may also represent a
structure where one or more other intermediate layers may exist
between the first layer and the second layer or the substrate.
Following implementations of the present disclosure are to provide
a semiconductor memory including a variable resistance element
having an improved performance and an electronic device including
the same. Here, the variable resistance element may mean an element
capable of being switched between different resistance states in
response to the applied bias (for example, a current or voltage).
Therefore, the variable resistance element having an improved
performance may mean the variable resistance element having an
improved switching characteristic between different resistance
states.
FIG. 1 is a cross-sectional view illustrating an exemplary variable
resistance element in accordance with an implementation of the
present disclosure, and FIG. 2 is a cross-sectional view
illustrating an exemplary variable resistance element in accordance
with another implementation of the implementation of the present
disclosure.
As shown in FIGS. 1 and 2, a variable resistance element 100 in
accordance with the implementation of the present disclosure may
include magnetic tunnel junction (MTJ) structure including a first
magnetic layer having a variable magnetization direction, a second
magnetic layer having a pinned magnetization direction, and a
tunnel barrier layer 130 interposed between the first magnetic
layer and the second magnetic layer. Here, the first magnetic layer
may be or include a free layer 120, and the second magnetic layer
may be or include a pinned layer 140.
In the MTJ structure, since the magnetization direction of the free
layer 120 is variable and can be changed by applying a current or a
voltage to the MTJ to cause the change, the resistance of or across
the MTJ varies as a variable resistance and exhibits different
resistance values depending on the relative direction of the
magnetization of the free layer 120 with respect to the fixed
magnetization direction of the pinned layer 140 so that the MTJ
exhibits different resistance states for different magnetization
directions of the free layer 120. Therefore, the different relative
directions of the magnetization directions of the free layer 120
and the pinned layer 140 can be used to represent different data or
data bits and, the free layer 120 may practically store data
according to its magnetization direction. Therefore, the free layer
120 may be referred to as a storage layer. The magnetization
direction of the free layer 120 may be changed by spin transfer
torque. Since the magnetization direction of the pinned layer 140
is pinned, the pinned layer 140 may be compared with the free layer
120 and be referred to as a reference layer. The tunnel barrier
layer 130 may serve to change the magnetization direction of the
free layer 120 by tunneling of electrons. In some implementations,
the free layer 120 and the pinned layer 140 may have the
magnetization direction perpendicular to a surface of each layer.
For example, as indicated by arrows in drawings, the magnetization
direction of the free layer 120 may be changed between a downward
direction and an upward direction, and the magnetization direction
of the pinned layer 140 may be fixed to an upward direction. In
other implementations, the free layer and the pinned layer may be
configured to have their magnetization directions to be parallel to
the layers in the MTJ.
In response to a voltage or current applied to the variable
resistance element 100, the magnetization direction of the free
layer 120 may be changed so as to be parallel or anti-parallel to
the magnetization direction of the pinned layer 140. As a result,
the variable resistance element 100 may be switched between a low
resistance state and a high resistance state to store different
data. That is, the variable resistance element 100 may function as
a memory cell.
Each of the free layer 120 and the pinned layer 140 may have a
single-layered structure or a multi-layered structure including a
ferromagnetic material. Here, the free layer 120 contacting with an
under layer 110 described below may have a BCC (Body Centered
Cubic) structure. Under this structural design, a magnetic
anisotropy of the free layer 120 may be improved due to the under
layer 110.
In some implementations, each of the free layer 120 and the pinned
layer 140 may include an alloy of which a main component is Fe, Ni
or Co, such as a Co--Fe--B alloy, a Co--Fe--B--X alloy (Here, X may
be or include Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag,
Hf, Ta, W or Pt.), an Fe--Pt alloy, an Fe--Pd alloy, a Co--Pd
alloy, a Co--Pt alloy, an Fe--Ni--Pt alloy, a Co--Fe--Pt alloy, a
Co--Ni--Pt alloy, an Fe--Pd alloy, a Co--Pd alloy, a Co--Pt alloy,
an Fe--Ni--Pt alloy, a Co--Fe--Pt alloy, or a Co--Ni--Pt alloy,
etc. Each of the free layer 120 and the pinned layer 140 may
include a stack structure of Co/Pt or Co/Pd, etc. or an alternate
stack structure of a magnetic material and a non-magnetic material.
The tunnel barrier layer 130 may include an insulating oxide, for
example, MgO, CaO, SrO, TiO, VO, or NbO, etc.
In some implementations, the variable resistance element 100 in
accordance with this implementation may further include one or more
additional layers performing various functions to improve a
characteristic of the MTJ structure. For example, one
implementation of the variable resistance element includes an under
layer 110, a spacer layer 150, a magnetic correction layer 160 and
a capping layer 170. However, the present disclosure is not limited
thereto and other implementations are also possible.
The under layer 110 may be used to improve a characteristic of the
layer disposed over the under layer 110, for example, the free
layer 120. This is because in part that the material of the free
layer 120 and the underlying material below the under layer 110
(e.g., a substrate) tend to be different materials with different
material structures and such difference can adversely affect the
final structure of the free layer 120. The under layer 110 is
specifically designed based on the such difference to provide an
interfacing structure to mitigate such adverse effect to the free
layer 120. Under this design, the characteristic improved by the
under layer 110 may be a magnetic anisotropy of the free layer 120.
The under layer 110 may include a plurality of material layers, and
each of the plurality of material layers may have a different
crystal structure from one another. Moreover, crystal structures of
the plurality of material layers may be different from a crystal
structure of the free layer 120. In some implementations, any one
of the plurality of material layers may include a dusting layer.
For the reference, "Dusting" in material science often means a
collection of particles or particle clusters that do not directly
bind with one another to form a continuous material layer or
structure. Instead, a "dusting layer" is a layer of particles or
particle clusters that are rather loosely located from one another
without any material bonding in between, more or less like a layer
of dust on a surface in a dirty room. For example, the dusting
layer may have a thin film having a very small thickness in an
atomic diameter or less. For example, the dusting layer may have a
thin film having a thickness of 1 nm or less. In some
implementations, the dusting layer may have a thin film in which
atoms are discontinuously arranged.
In some implementations, the under layer 110 may include a first
material layer 111, a second material layer 112 and a third
material layer 113, and the third material layer 113 may be or
include the dusting layer. The second material layer 112 may be
disposed over the first material layer 111, and the third material
layer 113 may be interposed between the first material layer 111
and the second material layer 112, such as the configuration in
FIG. 1. in which the free layer 120 is formed on top of the second
material layer 112 without being in direct contact with the dusting
layer 113 which is underneath the second material layer 112. In the
different configuration in FIG. 2, the dusting layer is located on
top of the first and second material layers 111 and 112 and is
between the second material layer 112 and the free layer 120 to be
directly under the free layer 120. Those two different
configurations for the under layer 110 are designed to provide an
interfacing material structure between the free layer 120 and the
material structure underneath the under layer 110.
The first material layer 111 may be used to improve a crystal
orientation with respect to the layer disposed over the first
material layer 111, for example, the second material layer 112. On
this account, the first material layer 111 may have an FCC (Face
Centered Cubic) crystal structure. In some implementations, the
first material layer 111 may include metal nitride having an FCC
crystal structure. For example, the first material layer 111 may
include zirconium nitride (ZrN), hafnium nitride (HfN), titanium
nitride (TiN), or molybdenum nitride (MoN).
The second material layer 112 may be used to improve a crystal
orientation with respect to the layer disposed over the second
material layer 112, for example, the free layer 120. On this
account, the second material layer 112 may have a NaCl crystal
structure. In some implementations, the second material layer 112
may include metal oxide having a NaCl crystal structure. For
example, the second material layer 112 may include magnesium oxide
(MgO) or zirconium oxide (ZrO).
The third material layer 113 may serve to reduce a lattice mismatch
between the layers disposed over and below the third material layer
113 in both designs in FIGS. 1 and 2 but have different roles in
the two different designs. For both designs, the third material
layer 113 may have a wurtzite crystal structure. In some
implementations, the third material layer 113 may include aluminum
nitride (AlN), silver iodide (AgI), zinc oxide (ZnO), cadmium
sulfate (CdS), cadmium selenide (CdSe), silicon carbide (SiC),
galium nitride (GaN) or boron nitride (BN), which have wurtzite
crystal structures.
Referring to the first implementation of the under layer 110 in
FIG. 1 in which the second material layer 112 is in direct contact
with the free layer 120 as shown in the sequentially stacked
structure for the variable resistance element 100, and the under
layer 110 with a multi-stack structure including the first material
layer 111, the third material layer 113 and the second material
layer 112, the third material layer 113 may serve to reduce a
lattice mismatch between the first material layer 111 and the
second material layer 112. That is, the third material layer 113
may serve to improve a crystal orientation of the whole structure
of the under layer 110. Since the under layer 110 may function as a
seed layer with respect to the free layer 120, a crystallinity of
the free layer 120 can be improved as a crystal orientation of the
under layer 110 is improved. As a result, a magnetic anisotropy of
the free layer 120 can be improved. In some implementations, when
the third material layer 113, which can be, for example, a dusting
layer, is interposed between the first material layer 111 and the
second material layer 112, the third material layer 113 preferably
has a thickness as large as possible within a predetermined range.
Here, the predetermined range may mean a thickness which enables
the third material layer 113 to function as the dusting layer, for
example, a thickness of 1 nm or less. This will be further
explained with reference to FIG. 3.
Then, referring to the second implementation of the under layer 110
in FIG. 2 where the third material layer 113 (e.g., a dusting
layer) is in direct contact with the free layer 120 as shown in the
sequentially stacked structure for the variable resistance element
100 and the multi-stack structure under layer 110 including the
first material layer 111, the second material layer 112 and the
third material layer 113, the third material layer 113 (e.g., a
dusting layer) may serve to reduce a lattice mismatch between the
second material layer 112 and the free layer 120. Thus, a lattice
mismatch can be decreased at the interface between the under layer
110 and the free layer 120 so as to improve a crystallinity of the
free layer 120. As a result, a magnetic anisotropy of the free
layer 120 can be improved. In some implementations, when the third
material layer 113, for example, the dusting layer is interposed
between the second material layer 112 and the free layer 120, the
third material layer 113 preferably has a thickness as small as
possible within a predetermined range. This will also be explained
with reference to FIG. 3.
The magnetic correction layer 160 may serve to offset or reduce an
influence of a stray field generated by the pinned layer 140. In
this case, the influence of the stray filed of the pinned layer 140
on the free layer 120 is decreased so that a bias magnetic field in
the free layer 120 can be reduced. The magnetic correction layer
160 may have a magnetization direction anti-parallel to the
magnetization direction of the pinned layer 140. In the
implementations, when the magnetization direction of the pinned
layer 140 is an upward direction, the magnetization direction of
the magnetic correction layer 160 may be a downward direction. On
the contrary, when the magnetization direction of the pinned layer
140 is a downward direction, the magnetization direction of the
magnetic correction layer 160 may be an upward direction.
Meanwhile, the magnetic correction layer 160 may have a
magnetization direction parallel to the magnetization direction of
the pinned layer 140.
The spacer layer 150 may be interposed between the magnetic
correction layer 160 and the pinned layer 140, and be used to
provide an interlayer exchange coupling therebetween. The spacer
layer 150 may include a metallic non-magnetic material such as Cr,
Ru, Ir, or Rh, etc.
The capping layer 170 may function as a hard mask for patterning
the variable resistance element 100. The capping layer 170 may
include various conductive materials such as a metal, etc.
The variable resistance element 100 in accordance with the
implementations of the present disclosure described above includes
the under layer 110 including the plurality of material layers
having different crystal structures so as to improve
characteristics of the variable resistance element 100.
FIG. 3 is a graph illustrating a change in a magnetic anisotropy
field in the free layer depending on a thickness of the dusting
layer in the variable resistance element in accordance with the
implementations of the present disclosure.
In FIG. 3, a horizontal axis represents a thickness of the dusting
layer, that is, a thickness of the third material layer 113, and a
vertical axis represents a normalized magnetic anisotropy field
(Hk) in the free layer 120. To obtain data necessary for FIG. 3,
aluminum nitride (AlN) has been used for the third material layer
113. The comparative example represents a case in which the under
layer 110 does not include the third material layer 113.
Referring to FIGS. 1 and 3, when the under layer 110 has a
multi-stack structure where the first material layer 111, the third
material layer 113 and the second material layer 112 are
sequentially stacked in a way that the second material layer 112 is
in direct contact with the free layer 120, it can be confirmed that
a magnetic anisotropy of the free layer 120 is improved as a
thickness of the third material layer 113 between the first and
second material layers 112 and 111 is increased within a thickness
range of the dusting layer, for example, from about 0.5 .ANG. to
about 2 .ANG.. The test results in FIG. 3 demonstrate this aspect
of the under layer 110 in FIG. 1.
In the other under layer design in FIG. 2 where the under layer 110
has a multi-stack structure having the first material layer 111,
the second material layer 112 and the third material layer 113 that
are sequentially stacked in a way that the third material layer 113
is directly underneath the free layer 120 and on top of the layers
111 and 112, it can be confirmed that a magnetic anisotropy of the
free layer 120 is improved as a thickness of the third material
layer 113 is decreased within a thickness range which may be
represented by the dusting layer, that is, within a predetermined
range. The test results in FIG. 3 demonstrate this aspect of the
under layer 110 in FIG. 1
From FIG. 3, it can be recognized that the magnetic anisotropy
field values of the free layer 120 differently change with a
thickness of the third material layer 113 depending on the position
of the third material layer 113. This is because a crystal
structure of the material layer disposed below the third material
layer 113 is changed depending on the position of the third
material layer 113. When the third material layer 113 is formed
over the first material layer 111, the first material layer 111
disposed below the third material layer 113 has an FCC crystal
structure. However, when the third material layer 113 is formed
over the second material layer 112, the second material layer 112
disposed below the third material layer 113 has a NaCl crystal
structure. As such, since the crystal structures of the material
layer disposed below the third material layer 113 are different
from each other, the crystallinity of the free layer 120 have been
affected by different influences in the two cases.
In accordance with implementation, it is possible to improve
characteristics of the variable resistance element and thus,
improve characteristics of the semiconductor memory including the
variable resistance element and the electronic device including the
semiconductor device.
The variable resistance element in accordance with the
implementations of the present disclosure, for example, the
variable resistance element 100 of FIG. 1 may be provided in plural
to form a cell array. The cell array may include various components
such as lines, or elements, etc. to drive the variable resistance
element 100. This will be exemplarily described with reference to
FIGS. 4 and 5.
FIG. 4 is a cross-sectional view illustrating an exemplary memory
device and a method for fabricating the same in accordance with an
implementation of the present disclosure.
Referring to FIG. 4, the memory device of this implementation may
include a substrate 500, a lower contact 520, a variable resistance
element 100 and an upper contact 550. The substrate 500 may include
a specific structure (not shown) which is required, for example, a
transistor controlling an access to the variable resistance element
100. The lower contact 520 may be disposed over the substrate 500,
and couple a lower end of the variable resistance element 100 with
a portion of the substrate 500, for example, a drain of the
transistor. The upper contact 550 may be disposed over the variable
resistance element 100, and couple an upper end of the variable
resistance element 100 with a certain line (not shown), for
example, a bit line.
The above memory device may be fabricated by following
processes.
First, the substrate 500 in which the transistor is formed may be
provided, and then, a first interlayer dielectric layer 510 may be
formed over the substrate 500. Subsequently, the lower contact 520
may be formed by selectively etching the first interlayer
dielectric layer 510 to form a hole exposing a portion of the
substrate 500 and filling the hole with a conductive material.
Then, the variable resistance element 100 may be formed by forming
material layers for the variable resistance element 100 over the
first interlayer dielectric layer 510 and the lower contact 520,
and selectively etching the material layers. A second interlayer
dielectric layer 530 may be formed by filling spaces among the
variable resistance elements 100 with an insulating material. Then,
a third interlayer dielectric layer 340 may be formed over the
variable resistance element 100 and the second interlayer
dielectric layer 530, and then, the upper contact 550 penetrating
through the third interlayer dielectric layer 530 and coupled to
the upper end of the variable resistance element 100 may be
formed.
In the memory device of this implementation, all layers included in
the variable resistance element 100 may have sidewalls aligned with
each other. This is because the variable resistance element 100 may
be formed by an etching process using a single mask.
However, unlike the implementation of FIG. 4, a portion of the
variable resistance element 100 and a remaining portion of the
variable resistance element 100 may be patterned individually. This
will be exemplarily shown in FIG. 5.
FIG. 5 is a cross-sectional view illustrating a memory device and a
method for fabricating the same in accordance with another
implementation of the present disclosure. Differences from the
implementation of FIG. 4 will be mainly described.
Referring to FIG. 5, in the memory device of this implementation, a
portion of the variable resistance element 100, for example, an
under layer 110 may have a sidewall which is not aligned with
sidewalls of remaining layers of the variable resistance element
100. The under layer 110 may have a sidewall which is aligned with
a sidewall of a lower contact 620.
The above memory device may be fabricated by following
processes.
First, a first interlayer dielectric layer 610 may be formed over a
substrate 600, and then, a hole H exposing a portion of the
substrate 600 may be formed by selectively etching the first
interlayer dielectric layer 610. Then, the lower contact 620 filled
in a lower portion of the hole H may be formed. Specifically, the
lower contact 620 may be formed by forming a conductive material
covering a resultant structure in which the hole H is formed, and
removing a portion of the conductive material by an etch back
process, etc, until the conductive material has a target height.
Then, the under layer 110 filled in a remaining space of the hole H
in which the lower contact 620 is formed may be formed. For
example, the under layer 110 may be formed by forming a material
layer which includes a light metal and covers a resultant structure
in which the lower contact 620 is formed, and performing a
planarization process, for example, a CMP (Chemical Mechanical
Polishing) process until a top surface of the first interlayer
dielectric layer 610 is exposed. Then, the remaining portion of the
variable resistance element 100 may be formed by forming material
layers for the remaining layers of the variable resistance element
100, except for the under layer 110, and selectively etching the
material layers. Following processes are substantially same as the
implementation of FIG. 4.
In this implementation, since a thickness to be etched for forming
the variable resistance element 100 decreases, a difficulty of an
etching process can be reduced.
Also, in this implementation, a case that the under layer 110 is
filled in the hole H is described. However, other implementations
are also possible. For example, another portion of the variable
resistance element 100 can be further filled in the hole H.
The semiconductor memory in accordance with the implementation of
the present disclosure may be applied to diverse electronic devices
or systems. FIGS. 6 to 10 show some examples of electronic devices
or systems that can implement the semiconductor memory disclosed
herein.
Referring to FIG. 6, a microprocessor 1000 may perform tasks for
controlling and tuning a series of processes of receiving data from
various external devices, processing the data, and outputting
processing results to external devices. The microprocessor 1000 may
include a memory unit 1010, an operation unit 1020, a control unit
1030, and so on. The microprocessor 1000 may be various data
processing units such as a central processing unit (CPU), a graphic
processing unit (GPU), a digital signal processor (DSP) and an
application processor (AP).
The memory unit 1010 is a part which stores data in the
microprocessor 1000, as a processor register, register or the like.
The memory unit 1010 may include a data register, an address
register, a floating point register and so on. Besides, the memory
unit 1010 may include various registers. The memory unit 1010 may
perform the function of temporarily storing data for which
operations are to be performed by the operation unit 1020, result
data of performing the operations and addresses where data for
performing of the operations are stored.
The memory unit 1010 may include one or more of the above-described
semiconductor devices in accordance with the implementations. The
memory unit 1010 may include semiconductor memory which includes a
variable resistance element. The variable resistance element may
include an under layer including a plurality of material layers,
each of the plurality of material layers having a different crystal
structure from each other, a first magnetic layer formed over the
under layer and having a variable magnetization direction, a tunnel
barrier layer formed over the first magnetic layer, and a second
magnetic layer formed over the tunnel barrier layer and having a
pinned magnetization direction. The under layer may include a first
material layer, a second material layer, and a third material layer
which have different crystal structures from each other, wherein
the third material layer may include a dusting layer. By providing
the under layer, it is possible to improve characteristics of the
variable resistance element. Therefore, the semiconductor memory
with improved operation characteristics may be provided. Through
this, the memory unit 1010 and the microprocessor 1000 may have
improved reliability.
The operation unit 1020 may perform four arithmetical operations or
logical operations according to results that the control unit 1030
decodes commands. The operation unit 1020 may include at least one
arithmetic logic unit (ALU) and so on.
The control unit 1030 may receive signals from the memory unit
1010, the operation unit 1020 and an external device of the
microprocessor 1000, perform extraction, decoding of commands, and
controlling input and output of signals of the microprocessor 1000,
and execute processing represented by programs.
The microprocessor 1000 according to the present implementation may
additionally include a cache memory unit 1040 which can temporarily
store data to be inputted from an external device other than the
memory unit 1010 or to be outputted to an external device. In this
case, the cache memory unit 1040 may exchange data with the memory
unit 1010, the operation unit 1020 and the control unit 1030
through a bus interface 1050.
FIG. 7 is an example of configuration diagram of a processor
implementing memory circuitry based on the disclosed
technology.
Referring to FIG. 7, a processor 1100 may improve performance and
realize multi-functionality by including various functions other
than those of a microprocessor which performs tasks for controlling
and tuning a series of processes of receiving data from various
external devices, processing the data, and outputting processing
results to external devices. The processor 1100 may include a core
unit 1110 which serves as the microprocessor, a cache memory unit
1120 which serves to storing data temporarily, and a bus interface
1130 for transferring data between internal and external devices.
The processor 1100 may include various system-on-chips (SoCs) such
as a multi-core processor, a graphic processing unit (GPU) and an
application processor (AP).
The core unit 1110 of the present implementation is a part which
performs arithmetic logic operations for data inputted from an
external device, and may include a memory unit 1111, an operation
unit 1112 and a control unit 1113.
The memory unit 1111 is a part which stores data in the processor
1100, as a processor register, a register or the like. The memory
unit 1111 may include a data register, an address register, a
floating point register and so on. Besides, the memory unit 1111
may include various registers. The memory unit 1111 may perform the
function of temporarily storing data for which operations are to be
performed by the operation unit 1112, result data of performing the
operations and addresses where data for performing of the
operations are stored. The operation unit 1112 is a part which
performs operations in the processor 1100. The operation unit 1112
may perform four arithmetical operations, logical operations,
according to results that the control unit 1113 decodes commands,
or the like. The operation unit 1112 may include at least one
arithmetic logic unit (ALU) and so on. The control unit 1113 may
receive signals from the memory unit 1111, the operation unit 1112
and an external device of the processor 1100, perform extraction,
decoding of commands, controlling input and output of signals of
processor 1100, and execute processing represented by programs.
The cache memory unit 1120 is a part which temporarily stores data
to compensate for a difference in data processing speed between the
core unit 1110 operating at a high speed and an external device
operating at a low speed. The cache memory unit 1120 may include a
primary storage section 1121, a secondary storage section 1122 and
a tertiary storage section 1123. In general, the cache memory unit
1120 includes the primary and secondary storage sections 1121 and
1122, and may include the tertiary storage section 1123 in the case
where high storage capacity is required. As the occasion demands,
the cache memory unit 1120 may include an increased number of
storage sections. That is to say, the number of storage sections
which are included in the cache memory unit 1120 may be changed
according to a design. The speeds at which the primary, secondary
and tertiary storage sections 1121, 1122 and 1123 store and
discriminate data may be the same or different. In the case where
the speeds of the respective storage sections 1121, 1122 and 1123
are different, the speed of the primary storage section 1121 may be
largest. At least one storage section of the primary storage
section 1121, the secondary storage section 1122 and the tertiary
storage section 1123 of the cache memory unit 1120 may include one
or more of the above-described semiconductor devices in accordance
with the implementations. For example, the cache memory unit 1120
may include semiconductor memory which includes a variable
resistance element. The variable resistance element may include an
under layer including a plurality of material layers, each of the
plurality of material layers having a different crystal structure
from each other, a first magnetic layer formed over the under layer
and having a variable magnetization direction, a tunnel barrier
layer formed over the first magnetic layer, and a second magnetic
layer formed over the tunnel barrier layer and having a pinned
magnetization direction. The under layer may include a first
material layer, a second material layer, and a third material layer
which have different crystal structures from each other, wherein
the third material layer may include a dusting layer. By providing
the under layer, it is possible to improve characteristics of the
variable resistance element. Therefore, the semiconductor memory
with improved operation characteristics may be provided. Through
this, the cache memory unit 1120 and the processor 1100 may have
improved reliability.
Although it was shown in FIG. 7 that all the primary, secondary and
tertiary storage sections 1121, 1122 and 1123 are configured inside
the cache memory unit 1120, it is to be noted that all the primary,
secondary and tertiary storage sections 1121, 1122 and 1123 of the
cache memory unit 1120 may be configured outside the core unit 1110
and may compensate for a difference in data processing speed
between the core unit 1110 and the external device. Meanwhile, it
is to be noted that the primary storage section 1121 of the cache
memory unit 1120 may be disposed inside the core unit 1110 and the
secondary storage section 1122 and the tertiary storage section
1123 may be configured outside the core unit 1110 to strengthen the
function of compensating for a difference in data processing speed.
In another implementation, the primary and secondary storage
sections 1121, 1122 may be disposed inside the core units 1110 and
tertiary storage sections 1123 may be disposed outside core units
1110.
The bus interface 1130 is a part which connects the core unit 1110,
the cache memory unit 1120 and external device and allows data to
be efficiently transmitted.
The processor 1100 according to the present implementation may
include a plurality of core units 1110, and the plurality of core
units 1110 may share the cache memory unit 1120. The plurality of
core units 1110 and the cache memory unit 1120 may be directly
connected or be connected through the bus interface 1130. The
plurality of core units 1110 may be configured in the same way as
the above-described configuration of the core unit 1110. In the
case where the processor 1100 includes the plurality of core unit
1110, the primary storage section 1121 of the cache memory unit
1120 may be configured in each core unit 1110 in correspondence to
the number of the plurality of core units 1110, and the secondary
storage section 1122 and the tertiary storage section 1123 may be
configured outside the plurality of core units 1110 in such a way
as to be shared through the bus interface 1130. The processing
speed of the primary storage section 1121 may be larger than the
processing speeds of the secondary and tertiary storage section
1122 and 1123. In another implementation, the primary storage
section 1121 and the secondary storage section 1122 may be
configured in each core unit 1110 in correspondence to the number
of the plurality of core units 1110, and the tertiary storage
section 1123 may be configured outside the plurality of core units
1110 in such a way as to be shared through the bus interface
1130.
The processor 1100 according to the present implementation may
further include an embedded memory unit 1140 which stores data, a
communication module unit 1150 which can transmit and receive data
to and from an external device in a wired or wireless manner, a
memory control unit 1160 which drives an external memory device,
and a media processing unit 1170 which processes the data processed
in the processor 1100 or the data inputted from an external input
device and outputs the processed data to an external interface
device and so on. Besides, the processor 1100 may include a
plurality of various modules and devices. In this case, the
plurality of modules which are added may exchange data with the
core units 1110 and the cache memory unit 1120 and with one
another, through the bus interface 1130.
The embedded memory unit 1140 may include not only a volatile
memory but also a nonvolatile memory. The volatile memory may
include a DRAM (dynamic random access memory), a mobile DRAM, an
SRAM (static random access memory), and a memory with similar
functions to above mentioned memories, and so on. The nonvolatile
memory may include a ROM (read only memory), a NOR flash memory, a
NAND flash memory, a phase change random access memory (PRAM), a
resistive random access memory (RRAM), a spin transfer torque
random access memory (STTRAM), a magnetic random access memory
(MRAM), a memory with similar functions.
The communication module unit 1150 may include a module capable of
being connected with a wired network, a module capable of being
connected with a wireless network and both of them. The wired
network module may include a local area network (LAN), a universal
serial bus (USB), an Ethernet, power line communication (PLC) such
as various devices which send and receive data through transmit
lines, and so on. The wireless network module may include Infrared
Data Association (IrDA), code division multiple access (CDMA), time
division multiple access (TDMA), frequency division multiple access
(FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN),
Bluetooth, radio frequency identification (RFID), long term
evolution (LTE), near field communication (NFC), a wireless
broadband Internet (Wibro), high speed downlink packet access
(HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB) such as
various devices which send and receive data without transmit lines,
and so on.
The memory control unit 1160 is to administrate and process data
transmitted between the processor 1100 and an external storage
device operating according to a different communication standard.
The memory control unit 1160 may include various memory
controllers, for example, devices which may control IDE (Integrated
Device Electronics), SATA (Serial Advanced Technology Attachment),
SCSI (Small Computer System Interface), RAID (Redundant Array of
Independent Disks), an SSD (solid state disk), eSATA (External
SATA), PCMCIA (Personal Computer Memory Card International
Association), a USB (universal serial bus), a secure digital (SD)
card, a mini secure digital (mSD) card, a micro secure digital
(micro SD) card, a secure digital high capacity (SDHC) card, a
memory stick card, a smart media (SM) card, a multimedia card
(MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so
on.
The media processing unit 1170 may process the data processed in
the processor 1100 or the data inputted in the forms of image,
voice and others from the external input device and output the data
to the external interface device. The media processing unit 1170
may include a graphic processing unit (GPU), a digital signal
processor (DSP), a high definition audio device (HD audio), a high
definition multimedia interface (HDMI) controller, and so on.
FIG. 8 is an example of configuration diagram of a system
implementing memory circuitry based on the disclosed
technology.
Referring to FIG. 8, a system 1200 as an apparatus for processing
data may perform input, processing, output, communication, storage,
etc. to conduct a series of manipulations for data. The system 1200
may include a processor 1210, a main memory device 1220, an
auxiliary memory device 1230, an interface device 1240, and so on.
The system 1200 of the present implementation may be various
electronic systems which operate using processors, such as a
computer, a server, a PDA (personal digital assistant), a portable
computer, a web tablet, a wireless phone, a mobile phone, a smart
phone, a digital music player, a PMP (portable multimedia player),
a camera, a global positioning system (GPS), a video camera, a
voice recorder, a telematics, an audio visual (AV) system, a smart
television, and so on.
The processor 1210 may decode inputted commands and processes
operation, comparison, etc. for the data stored in the system 1200,
and controls these operations. The processor 1210 may include a
microprocessor unit (MPU), a central processing unit (CPU), a
single/multi-core processor, a graphic processing unit (GPU), an
application processor (AP), a digital signal processor (DSP), and
so on.
The main memory device 1220 is a storage which can temporarily
store, call and execute program codes or data from the auxiliary
memory device 1230 when programs are executed and can conserve
memorized contents even when power supply is cut off. The main
memory device 1220 may include one or more of the above-described
semiconductor devices in accordance with the implementations. For
example, the main memory device 1220 may include semiconductor
memory which includes a variable resistance element. The variable
resistance element may include an under layer including a plurality
of material layers, each of the plurality of material layers having
a different crystal structure from each other, a first magnetic
layer formed over the under layer and having a variable
magnetization direction, a tunnel barrier layer formed over the
first magnetic layer, and a second magnetic layer formed over the
tunnel barrier layer and having a pinned magnetization direction.
The under layer may include a first material layer, a second
material layer, and a third material layer which have different
crystal structures from each other, wherein the third material
layer may include a dusting layer. By providing the under layer, it
is possible to improve characteristics of the variable resistance
element. Therefore, the semiconductor memory with improved
operation characteristics may be provided. Through this, the main
memory device 1220 and the system 1200 may have improved
reliability.
Also, the main memory device 1220 may further include a static
random access memory (SRAM), a dynamic random access memory (DRAM),
and so on, of a volatile memory type in which all contents are
erased when power supply is cut off. Unlike this, the main memory
device 1220 may not include the semiconductor devices according to
the implementations, but may include a static random access memory
(SRAM), a dynamic random access memory (DRAM), and so on, of a
volatile memory type in which all contents are erased when power
supply is cut off.
The auxiliary memory device 1230 is a memory device for storing
program codes or data. While the speed of the auxiliary memory
device 1230 is slower than the main memory device 1220, the
auxiliary memory device 1230 can store a larger amount of data. The
auxiliary memory device 1230 may include one or more of the
above-described semiconductor devices in accordance with the
implementations. For example, the auxiliary memory device 1230 may
include semiconductor memory which includes a variable resistance
element. The variable resistance element may include an under layer
including a plurality of material layers, each of the plurality of
material layers having a different crystal structure from each
other, a first magnetic layer formed over the under layer and
having a variable magnetization direction, a tunnel barrier layer
formed over the first magnetic layer, and a second magnetic layer
formed over the tunnel barrier layer and having a pinned
magnetization direction. The under layer may include a first
material layer, a second material layer, and a third material layer
which have different crystal structures from each other, wherein
the third material layer may include a dusting layer. By providing
the under layer, it is possible to improve characteristics of the
variable resistance element. Therefore, the semiconductor memory
with improved operation characteristics may be provided. Through
this, the auxiliary memory device 1230 and the system 1200 may have
improved reliability.
Also, the auxiliary memory device 1230 may further include a data
storage system (see the reference numeral 1300 of FIG. 9) such as a
magnetic tape using magnetism, a magnetic disk, a laser disk using
optics, a magneto-optical disc using both magnetism and optics, a
solid state disk (SSD), a USB memory (universal serial bus memory),
a secure digital (SD) card, a mini secure digital (mSD) card, a
micro secure digital (micro SD) card, a secure digital high
capacity (SDHC) card, a memory stick card, a smart media (SM) card,
a multimedia card (MMC), an embedded MMC (eMMC), a compact flash
(CF) card, and so on. Unlike this, the auxiliary memory device 1230
may not include the semiconductor devices according to the
implementations, but may include data storage systems (see the
reference numeral 1300 of FIG. 9) such as a magnetic tape using
magnetism, a magnetic disk, a laser disk using optics, a
magneto-optical disc using both magnetism and optics, a solid state
disk (SSD), a USB memory (universal serial bus memory), a secure
digital (SD) card, a mini secure digital (mSD) card, a micro secure
digital (micro SD) card, a secure digital high capacity (SDHC)
card, a memory stick card, a smart media (SM) card, a multimedia
card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and
so on.
The interface device 1240 may be to perform exchange of commands
and data between the system 1200 of the present implementation and
an external device. The interface device 1240 may be a keypad, a
keyboard, a mouse, a speaker, a mike, a display, various human
interface devices (HIDs), a communication device, and so on. The
communication device may include a module capable of being
connected with a wired network, a module capable of being connected
with a wireless network and both of them. The wired network module
may include a local area network (LAN), a universal serial bus
(USB), an Ethernet, power line communication (PLC), such as various
devices which send and receive data through transmit lines, and so
on. The wireless network module may include Infrared Data
Association (IrDA), code division multiple access (CDMA), time
division multiple access (TDMA), frequency division multiple access
(FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN),
Bluetooth, radio frequency identification (RFID), long term
evolution (LTE), near field communication (NFC), a wireless
broadband Internet (Wibro), high speed downlink packet access
(HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), such as
various devices which send and receive data without transmit lines,
and so on.
FIG. 9 is an example of configuration diagram of a data storage
system implementing memory circuitry based on the disclosed
technology.
Referring to FIG. 9, a data storage system 1300 may include a
storage device 1310 which has a nonvolatile characteristic as a
component for storing data, a controller 1320 which controls the
storage device 1310, an interface 1330 for connection with an
external device, and a temporary storage device 1340 for storing
data temporarily. The data storage system 1300 may be a disk type
such as a hard disk drive (HDD), a compact disc read only memory
(CDROM), a digital versatile disc (DVD), a solid state disk (SSD),
and so on, and a card type such as a USB memory (universal serial
bus memory), a secure digital (SD) card, a mini secure digital
(mSD) card, a micro secure digital (micro SD) card, a secure
digital high capacity (SDHC) card, a memory stick card, a smart
media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a
compact flash (CF) card, and so on.
The storage device 1310 may include a nonvolatile memory which
stores data semi-permanently. The nonvolatile memory may include a
ROM (read only memory), a NOR flash memory, a NAND flash memory, a
phase change random access memory (PRAM), a resistive random access
memory (RRAM), a magnetic random access memory (MRAM), and so
on.
The controller 1320 may control exchange of data between the
storage device 1310 and the interface 1330. To this end, the
controller 1320 may include a processor 1321 for performing an
operation for, processing commands inputted through the interface
1330 from an outside of the data storage system 1300 and so on.
The interface 1330 is to perform exchange of commands and data
between the data storage system 1300 and the external device. In
the case where the data storage system 1300 is a card type, the
interface 1330 may be compatible with interfaces which are used in
devices, such as a USB memory (universal serial bus memory), a
secure digital (SD) card, a mini secure digital (mSD) card, a micro
secure digital (micro SD) card, a secure digital high capacity
(SDHC) card, a memory stick card, a smart media (SM) card, a
multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF)
card, and so on, or be compatible with interfaces which are used in
devices similar to the above mentioned devices. In the case where
the data storage system 1300 is a disk type, the interface 1330 may
be compatible with interfaces, such as IDE (Integrated Device
Electronics), SATA (Serial Advanced Technology Attachment), SCSI
(Small Computer System Interface), eSATA (External SATA), PCMCIA
(Personal Computer Memory Card International Association), a USB
(universal serial bus), and so on, or be compatible with the
interfaces which are similar to the above mentioned interfaces. The
interface 1330 may be compatible with one or more interfaces having
a different type from each other.
The temporary storage device 1340 can store data temporarily for
efficiently transferring data between the interface 1330 and the
storage device 1310 according to diversifications and high
performance of an interface with an external device, a controller
and a system. The temporary storage device 1340 for temporarily
storing data may include one or more of the above-described
semiconductor devices in accordance with the implementations. For
example, the temporary storage device 1340 may include
semiconductor memory which includes a variable resistance element.
The variable resistance element may include an under layer
including a plurality of material layers, each of the plurality of
material layers having a different crystal structure from each
other, a first magnetic layer formed over the under layer and
having a variable magnetization direction, a tunnel barrier layer
formed over the first magnetic layer, and a second magnetic layer
formed over the tunnel barrier layer and having a pinned
magnetization direction. The under layer may include a first
material layer, a second material layer, and a third material layer
which have different crystal structures from each other, wherein
the third material layer may include a dusting layer. By providing
the under layer, it is possible to improve characteristics of the
variable resistance element. Therefore, the semiconductor memory
with improved operation characteristics may be provided. Through
this, the temporary storage device 1340 and the data storage system
1300 may have improved reliability.
FIG. 10 is an example of configuration diagram of a memory system
implementing memory circuitry based on the disclosed
technology.
Referring to FIG. 10, a memory system 1400 may include a memory
1410 which has a nonvolatile characteristic as a component for
storing data, a memory controller 1420 which controls the memory
1410, an interface 1430 for connection with an external device, and
so on. The memory system 1400 may be a card type such as a solid
state disk (SSD), a USB memory (universal serial bus memory), a
secure digital (SD) card, a mini secure digital (mSD) card, a micro
secure digital (micro SD) card, a secure digital high capacity
(SDHC) card, a memory stick card, a smart media (SM) card, a
multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF)
card, and so on.
The memory 1410 for storing data may include one or more of the
above-described semiconductor devices in accordance with the
implementations. For example, the memory 1410 may include
semiconductor memory which includes a variable resistance element.
The variable resistance element may include an under layer
including a plurality of material layers, each of the plurality of
material layers having a different crystal structure from each
other, a first magnetic layer formed over the under layer and
having a variable magnetization direction, a tunnel barrier layer
formed over the first magnetic layer, and a second magnetic layer
formed over the tunnel barrier layer and having a pinned
magnetization direction. The under layer may include a first
material layer, a second material layer, and a third material layer
which have different crystal structures from each other, wherein
the third material layer may include a dusting layer. By providing
the under layer, it is possible to improve characteristics of the
variable resistance element. Therefore, the semiconductor memory
with improved operation characteristics may be provided. Through
this, the memory 1410 and the memory system 1400 may have improved
reliability.
Also, the memory 1410 according to the present implementation may
further include a ROM (read only memory), a NOR flash memory, a
NAND flash memory, a phase change random access memory (PRAM), a
resistive random access memory (RRAM), a magnetic random access
memory (MRAM), and so on, which have a nonvolatile
characteristic.
The memory controller 1420 may control exchange of data between the
memory 1410 and the interface 1430. To this end, the memory
controller 1420 may include a processor 1421 for performing an
operation for and processing commands inputted through the
interface 1430 from an outside of the memory system 1400.
The interface 1430 is to perform exchange of commands and data
between the memory system 1400 and the external device. The
interface 1430 may be compatible with interfaces which are used in
devices, such as a USB memory (universal serial bus memory), a
secure digital (SD) card, a mini secure digital (mSD) card, a micro
secure digital (micro SD) card, a secure digital high capacity
(SDHC) card, a memory stick card, a smart media (SM) card, a
multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF)
card, and so on, or be compatible with interfaces which are used in
devices similar to the above mentioned devices. The interface 1430
may be compatible with one or more interfaces having a different
type from each other.
The memory system 1400 according to the present implementation may
further include a buffer memory 1440 for efficiently transferring
data between the interface 1430 and the memory 1410 according to
diversification and high performance of an interface with an
external device, a memory controller and a memory system. For
example, the buffer memory 1440 may include semiconductor memory
which includes a variable resistance element. The variable
resistance element may include an under layer including a plurality
of material layers, each of the plurality of material layers having
a different crystal structure from each other, a first magnetic
layer formed over the under layer and having a variable
magnetization direction, a tunnel barrier layer formed over the
first magnetic layer, and a second magnetic layer formed over the
tunnel barrier layer and having a pinned magnetization direction.
The under layer may include a first material layer, a second
material layer, and a third material layer which have different
crystal structures from each other, wherein the third material
layer may include a dusting layer. By providing the under layer, it
is possible to improve characteristics of the variable resistance
element. Therefore, the semiconductor memory with improved
operation characteristics may be provided. Through this, the buffer
memory 1440 and the memory system 1400 may have improved
reliability.
Moreover, the buffer memory 1440 according to the present
implementation may further include an SRAM (static random access
memory), a DRAM (dynamic random access memory), and so on, which
have a volatile characteristic, and a phase change random access
memory (PRAM), a resistive random access memory (RRAM), a spin
transfer torque random access memory (STTRAM), a magnetic random
access memory (MRAM), and so on, which have a nonvolatile
characteristic. Unlike this, the buffer memory 1440 may not include
the semiconductor devices according to the implementations, but may
include an SRAM (static random access memory), a DRAM (dynamic
random access memory), and so on, which have a volatile
characteristic, and a phase change random access memory (PRAM), a
resistive random access memory (RRAM), a spin transfer torque
random access memory (STTRAM), a magnetic random access memory
(MRAM), and so on, which have a nonvolatile characteristic.
Features in the above examples of electronic devices or systems in
FIGS. 11 to 15 based on the memory devices disclosed in this
document may be implemented in various devices, systems or
applications. Some examples include mobile phones or other portable
communication devices, tablet computers, notebook or laptop
computers, game machines, smart TV sets, TV set top boxes,
multimedia servers, digital cameras with or without wireless
communication functions, wrist watches or other wearable devices
with wireless communication capabilities.
While this patent document contains many specifics, these should
not be construed as limitations on the scope of any invention or of
what may be claimed, but rather as descriptions of features that
may be specific to particular embodiments of particular inventions.
Certain features that are described in this patent document in the
context of separate embodiments can also be implemented in
combination in a single embodiment. Conversely, various features
that are described in the context of a single embodiment can also
be implemented in multiple embodiments separately or in any
suitable subcombination. Moreover, although features may be
described above as acting in certain combinations and even
initially claimed as such, one or more features from a claimed
combination can in some cases be excised from the combination, and
the claimed combination may be directed to a subcombination or
variation of a subcombination.
Similarly, while operations are depicted in the drawings in a
particular order, this should not be understood as requiring that
such operations be performed in the particular order shown or in
sequential order, or that all illustrated operations be performed,
to achieve desirable results. Moreover, the separation of various
system components in the embodiments described in this patent
document should not be understood as requiring such separation in
all embodiments.
Only a few implementations and examples are described. Other
implementations, enhancements and variations can be made based on
what is described and illustrated in this patent document.
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