U.S. patent application number 14/814524 was filed with the patent office on 2017-02-02 for multi-device package and manufacturing method thereof.
The applicant listed for this patent is Inotera Memories, Inc.. Invention is credited to Shih-Fan KUAN, Yi-Jen LO.
Application Number | 20170033078 14/814524 |
Document ID | / |
Family ID | 57705872 |
Filed Date | 2017-02-02 |
United States Patent
Application |
20170033078 |
Kind Code |
A1 |
KUAN; Shih-Fan ; et
al. |
February 2, 2017 |
MULTI-DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF
Abstract
A multi-device package includes a substrate, at least two device
regions, a first redistribution layer, an external chip, a
plurality of first connectors and a conductive contact. The two
device regions are formed from the substrate, and the substrate has
a first surface and a second surface opposite to the first surface.
The first redistribution layer is disposed on the first surface and
electrically connected to the two device regions, and the external
chip is disposed on the first redistribution layer. The first
connectors are interposed between the first redistribution layer
and the external chip to interconnect the first redistribution
layer and the external chip, and the conductive contact is extended
from the second surface to the first surface of the substrate to
electrically connect the device region.
Inventors: |
KUAN; Shih-Fan; (Taoyuan
City, TW) ; LO; Yi-Jen; (New Taipei City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Inotera Memories, Inc. |
Taoyuan City |
|
TW |
|
|
Family ID: |
57705872 |
Appl. No.: |
14/814524 |
Filed: |
July 31, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/81815
20130101; H01L 23/525 20130101; H01L 2224/97 20130101; H01L 21/6835
20130101; H01L 24/13 20130101; H01L 24/97 20130101; H01L 24/17
20130101; H01L 2224/13025 20130101; H01L 2224/94 20130101; H01L
2225/06513 20130101; H01L 23/522 20130101; H01L 23/5386 20130101;
H01L 21/823475 20130101; H01L 25/50 20130101; H01L 2224/11849
20130101; H01L 2224/16145 20130101; H01L 2224/9202 20130101; H01L
2224/13111 20130101; H01L 2224/81 20130101; H01L 23/49816 20130101;
H01L 21/561 20130101; H01L 24/16 20130101; H01L 21/6836 20130101;
H01L 2224/131 20130101; H01L 2225/06517 20130101; H01L 2224/16227
20130101; H01L 2224/9202 20130101; H01L 2924/3511 20130101; H01L
23/3114 20130101; H01L 23/562 20130101; H01L 2221/6834 20130101;
H01L 23/481 20130101; H01L 2224/0401 20130101; H01L 2224/94
20130101; H01L 2224/14181 20130101; H01L 2224/94 20130101; H01L
25/0657 20130101; H01L 2221/68327 20130101; H01L 2224/97 20130101;
H01L 2224/131 20130101; H01L 2225/06541 20130101; H01L 2224/81
20130101; H01L 2924/00014 20130101; H01L 2924/014 20130101; H01L
2924/014 20130101; H01L 2224/11 20130101; H01L 2224/11 20130101;
H01L 2224/131 20130101; H01L 21/52 20130101; H01L 2924/1434
20130101; H01L 2224/17181 20130101; H01L 24/94 20130101; H01L
2221/68381 20130101; H01L 2225/06568 20130101 |
International
Class: |
H01L 25/065 20060101
H01L025/065; H01L 23/538 20060101 H01L023/538; H01L 23/31 20060101
H01L023/31; H01L 21/8234 20060101 H01L021/8234; H01L 25/00 20060101
H01L025/00; H01L 21/52 20060101 H01L021/52; H01L 21/56 20060101
H01L021/56; H01L 21/768 20060101 H01L021/768; H01L 23/00 20060101
H01L023/00; H01L 23/522 20060101 H01L023/522 |
Claims
1. A multi-device package, comprising: at least two device regions
formed from a substrate, and the substrate having a first surface
and a second surface opposite to the first surface; a first
redistribution layer disposed on the first surface and electrically
connected to the two device regions; an external chip disposed on
the first redistribution layer and at least electrically connected
to the two device regions by the first redistribution layer; a
plurality of first connectors interposed between the first
redistribution layer and the external chip to interconnect the two;
and a conductive contact extending from the second surface to the
first surface of the substrate to electrically connect the device
region.
2. The multi-device package of claim 1, further comprising a
plurality of second connectors below the second surface, and each
of the second connectors being in contact with the conductive
contact.
3. The multi-device package of claim 1, further comprising a
molding layer covering the external chip and the first
redistribution layer.
4. The multi-device package of claim 2, wherein a diameter of the
second connector is larger than a diameter of the first
connector.
5. The multi-device package of claim 2, wherein the first
connectors and the second connectors are solder bumps or solder
balls.
6. The multi-device package of claim 1, further comprising: second
redistribution layer disposed below the second surface; and a
plurality of second connectors disposed below the second
redistribution layer.
7. The multi-device package of claim 6, wherein each of the first
redistribution layer and the second redistribution layer comprises:
a plurality of metal layers arranged in parallel inside a
dielectric layer; and a plurality of vias, and the two adjacent
metal layers being electrically connected by the via.
8. The multi-device package of claim 1, wherein the device region
comprises: a semiconductor device; an inter-layer dielectric layer
covering the semiconductor device; an inter-metal dielectric layer
on the inter-layer dielectric layer; and a metal interconnect
structure through the inter-metal dielectric layer and the
inter-layer dielectric layer, and an uppermost metal layer of the
metal interconnect structure acting as a conductive pad of the
device region.
9. The multi-device package of claim 8, wherein the conductive
contact is in contact with the conductive pad of the device
region.
10. The multi-device package of claim 8, wherein the semiconductor
device is a memory device.
11. A multi-device package, comprising: at least two device regions
disposed in a substrate; a first redistribution layer disposed on
the substrate; an external chip disposed on the first
redistribution layer and at least electrically connected to the two
device regions by the first redistribution layer; a second
redistribution layer disposed below the substrate; and a conductive
contact through the device region to interconnect the second
redistribution layer and the device region.
12. A process of manufacturing, a multi-device package, comprising:
providing a wafer having a first surface and a second surface
opposite to the first surface, and the wafer having at least two
device regions therein; forming a first redistribution layer on the
first surface, and the first redistribution layer being
electrically connected to the two device regions; forming a
plurality of first connectors on the first redistribution layer;
mounting an external chip on the first connectors, and the external
chip being at least electrically connected to the two device
regions by the first redistribution layer and first connectors; and
forming a conductive contact extending from the second surface to
the first surface, and the conductive contact being electrically
connected to the device regions.
13. The process of manufacturing the multi-device package of claim
12, further comprising: forming a molding layer covering the
external chip; forming a temporary adhesive layer on the molding
layer; thinning the wafer; and removing the temporary adhesive
layer.
14. The process of manufacturing the multi-device package of claim
13, flintier comprising: forming a plurality of second connectors
below the second surface, and a diameter of the second connector
being larger than a diameter of the first connector.
15. The process of manufacturing the multi-device package of claim
14, further comprising: dicing the wafer along a scribe line to
form the multi-device package.
16. The process of manufacturing the multi-device package of claim
12, wherein forming the conductive contact extending from the
second surface to the first surface comprises: removing a portion
of the wafer to form a through hole exposing a conductive pad of
the device region; and filling a conductive material in the through
holes to form the conductive contact.
17. The process of manufacturing the multi-device package of claim
13, further comprising: forming a second redistribution layer below
the second surface, and the second redistribution layer being
electrically connected to the conductive contact; and forming a
plurality of second connectors below the second redistribution
layer.
18. The process of manufacturing the multi-device package of claim
17, further comprising: dicing the wafer along a scribe line to
form the multi-device package.
19. The process of manufacturing the multi-device package of claim
12, wherein forming the first redistribution layer on the first
surface comprises: depositing a dielectric material covering the
first surface; removing a portion of the dielectric material to
form openings exposing the device regions of the wafer; forming
vias in the openings; forming a metal layer on the vias; and
patterning the metal layer.
20. The process of manufacturing the multi-device package of claim
17, wherein forming the second redistribution layer below the
second surface comprises: forming a dielectric material covering
the second surface; removing a portion of the dielectric material
to form openings exposing the conductive contact; forming vias in
the openings; forming a metal layer below the vias; and patterning
the metal layer.
Description
BACKGROUND
Description of Related Art
[0001] Along the evolution in the manufacturing technology of the
semiconductor devices, the functional density of the semiconductor
devices has increased with the decrease of device sizes to achieve
higher integration density of the semiconductor devices. As a
result, the demands to the packaging technology are becoming severe
under the condition of decrease in size and increase in density of
the semiconductor devices. In recent years, the demands to the
smaller electronic devices have increased, and innovative packaging
technology is required.
[0002] Generally, several devices are fabricated in a wafer, and a
dicing process is performed to separate these devices into
individual chips. These chips are placed on a carrier substrate,
and a packaging process is performed to integrate multiple chips in
one package. However, these chips suffer vibration when being
placed on the carrier substrate, and problems of disconnection and
fracture may easily occur on the chips, which decrease the yield of
the package. In addition, extra costs for the carrier substrate
further decrease efficiency of the packaging process. Therefore, a
novel packaging structure and a manufacturing process thereof are
necessary to solve problems mentioned above.
SUMMARY
[0003] The present disclosure provides a multi-device package. The
multi-device package includes a substrate, at least two device
regions, a first redistribution layer, an external chip, a
plurality of first connectors and a conductive contact. The two
device regions are formed from the substrate, and the substrate
having a first surface and a second surface opposite to the first
surface. The first redistribution layer is disposed on the first
surface and electrically connected to the two device regions, and
the external chip is disposed on the first redistribution layer.
The first connectors are interposed between the first
redistribution layer and the external chip to interconnect the
first redistribution layer and the external chip, and the
conductive contact is extended from the second surface to the first
surface of the substrate to electrically connect the device
region.
[0004] In various embodiments of the present disclosure, the
multi-device package further includes a plurality of second
connectors below the second surface, and each of the second
connectors is in contact with the conductive contact.
[0005] In various embodiments of the present disclosure, the
multi-device package further includes a molding layer covering the
external chip and the first redistribution layer.
[0006] In various embodiments of the present disclosure, a diameter
of the second connector is larger than a diameter of the first
connector.
[0007] In various embodiments of the present disclosure, the first
connectors and the second connectors are solder bumps or solder
balls.
[0008] In various embodiments of the present disclosure, the
multi-device package further includes a second redistribution layer
and a plurality of second connectors. The second redistribution
layer is disposed below the second surface, and the second
connectors are disposed below the second redistribution layer.
[0009] In various embodiments of the present disclosure, each of
the first redistribution layer and the second redistribution layer
includes a dielectric layer, a plurality of metal layers and a
plurality of vias. The metal layers are arranged in parallel inside
the dielectric layer, and the two adjacent metal layers are
electrically connected by the via.
[0010] In various embodiments of the present disclosure, the device
region includes a semiconductor device, an inter-layer dielectric
layer, an inter-metal dielectric layer and a metal interconnect
structure. The inter-layer dielectric layer covers the
semiconductor device, and the inter-metal dielectric layer is on
the inter-layer dielectric layer. The metal interconnect structure
is through the inter-metal dielectric layer and the inter-layer
dielectric layer, and an uppermost metal layer of the metal
interconnect structure acts as a conductive pad of the device
region.
[0011] In various embodiments of the present disclosure, the
conductive contact is in contact with the conductive pad of the
device region.
[0012] In various embodiments of the present disclosure, the
semiconductor device is a memory device.
[0013] The present disclosure provides a multi-device package. The
multi-device package includes a substrate, at least two device
regions, a first redistribution layer, an external chip, a second
redistribution layer and a conductive contact. The two device
regions are disposed in the substrate, and the first redistribution
layer is disposed on the substrate. The external chip is disposed
on the first redistribution layer, and the second redistribution
layer is disposed below the substrate. The conductive contact is
through the device region to interconnect the second redistribution
layer and the device region.
[0014] The present disclosure provides a process of manufacturing a
multi-device package, and the process includes following steps. A
wafer having a first surface and a second surface opposite to the
first surface is provided, and the wafer has at least two device
regions therein. A first redistribution layer is formed on the
first surface, which the first redistribution layer is electrically
connected to the two device regions. Then, a plurality of first
connectors is formed on the first redistribution layer; and an
external chip is mounted on the first connectors, which the
external chip is electrically connected to the first redistribution
layer by the first connectors. A conductive contact is formed to
extend from the second surface to the first surface, and the
conductive contact is electrically connected to the device
regions.
[0015] In various embodiments of the present disclosure, the
process further includes following steps. A molding layer is formed
to cover the external chip, and a temporary adhesive layer is
formed on the molding layer. Then, the wafer is thinned, and the
temporary adhesive layer is removed.
[0016] In various embodiments of the present disclosure, the
process further includes following steps. A plurality of second
connectors is formed below the second surface, and a diameter of
the second connector is larger than a diameter of the first
connector.
[0017] In various embodiments of the present disclosure, the
process further includes dicing the wafer along a scribe line to
form the multi-device package.
[0018] In various embodiments of the present disclosure, the
conductive contact is formed to extend from the second surface to
the first surface by following steps. A portion of the wafer is
removed to form a through hole exposing a conductive pad of the
device region, and a conductive material is filled in the through
holes to form the conductive contact.
[0019] In various embodiments of the present disclosure, the
process further includes following steps. A second redistribution
layer is formed below the second surface, and the second
redistribution layer is electrically connected to the conductive
contact. Then, a plurality of second connectors is formed below the
second redistribution layer.
[0020] In various embodiments of the present disclosure, the
process further includes dicing the wafer along a scribe line to
form the multi-device package.
[0021] In various embodiments of the present disclosure, the first
redistribution layer is formed on the first surface by following
steps. A dielectric material covering is deposited to cover the
first surface, and a portion of the dielectric material is removed
to form openings exposing the device regions of the wafer. Vias are
formed in the openings, and a metal layer is formed on the vias.
Then, the metal layer is patterned.
[0022] In various embodiments of the present disclosure, the second
redistribution layer is formed below the second surface by
following steps. A dielectric material covering is deposited to
cover the second surface, and a portion of the dielectric material
is removed to form openings exposing the conductive contact. Vias
are formed in the openings, and a metal layer is formed below the
vias. Then, the metal layer is patterned.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The disclosure could be more fully understood by reading the
following detailed description of the embodiment, with reference
made to the accompanying drawings as follows:
[0024] FIG. 1A is a top view of a multi-device package according to
various embodiments of the present disclosure;
[0025] FIG. 1B is a bottom view of a multi-device package according
to various embodiments of the present disclosure;
[0026] FIG. 1C is a cross-sectional view of the multi-device
package in FIGS. 1A and 1B along the line AA, according to various
embodiments of the present disclosure;
[0027] FIG. 1D is an enlarged view of the device region in the
multi-device package;
[0028] FIG. 2A is a top view of a multi-device package according to
various embodiments of the present disclosure;
[0029] FIG. 2B is a bottom view of a multi-device package according
to various embodiments of the present disclosure;
[0030] FIG. 2C is a cross-sectional view of the multi-device
package in FIGS. 2A and 2B along the line AA, according to various
embodiments of the present disclosure;
[0031] FIGS. 3A to 3E are cross-sectional views of the multi-device
package in FIGS. 1A to 1C at an intermediate stage of fabrication,
in accordance with various embodiments; and
[0032] FIGS. 4A to 4F are cross-sectional views of the multi-device
package in FIGS. 2A to 2C at an intermediate stage of fabrication,
in accordance with various embodiments.
DETAILED DESCRIPTION
[0033] Reference will now be made in detail to the present
embodiments of the invention, examples of which are illustrated in
the accompanying drawings. Wherever possible, the same reference
numbers are used in the drawings and the description to refer to
the same or like parts.
[0034] The following embodiments are disclosed with accompanying
diagrams for detailed description. For illustration clarity, many
details of practice are explained in the following descriptions.
However, it should be understood that these details of practice do
not intend to limit the present invention. That is, these details
of practice are not necessary in parts of embodiments of the
present invention. Furthermore, for simplifying the drawings, some
of the conventional structures and elements are shown with
schematic illustrations.
[0035] Please refer to FIG. 1A, FIG. 1B and FIG. 1C at the same
time. FIG. 1A is a top view of a multi-device package according to
various embodiments of the present disclosure, FIG. 1B is a bottom
view of a multi-device package according to various embodiments of
the present disclosure, and FIG. 1C is a cross-sectional view of
the multi-device package in FIGS. 1A and 1B along the line AA,
according to various embodiments of the present disclosure. As
shown in FIG. 10, a multi-device package 100 includes a substrate
110, at least two device regions 120, a first redistribution layer
130, an external chip 140, a plurality of first connectors 150 and
a plurality of second connectors 160. The substrate 110 includes a
first surface 112 and a second surface 114, which the first surface
112 is opposite to the second surface 114.
[0036] These device regions 120 are formed from the substrate 110,
so there is no interface between the device regions 120 and the
substrate 110. Generally, a wafer is diced to separate device
regions into individual chips. These chips are placed on a carrier
substrate, and an interface is formed between the carrier substrate
and the chips. Then, a packaging process is performed to integrate
multiple chips in one package. However, these chips suffer
vibration when being placed on the carrier substrate, and problems
of disconnection and fracture may easily occur on the chips, which
decrease the yield of the package. In addition, extra costs for the
carrier substrate further decrease efficiency of the packaging
process. Relatively, the multi-device package 100 of the present
disclosure is manufactured by a wafer-level packaging process,
which means all the device regions 120 are packaged and tested
after completion of manufacturing these device regions 120 in the
wafer, and then the wafer is diced into the multi-device package
100 shown in FIG. 1A to 1C. It is worth noting that the device
regions 120 in the wafer are integrated directly before dicing to
omit the usage of the carrier substrate, so that the device regions
120 and the substrate 110 have no interface therebetween.
[0037] Referring to FIG. 1D at the same time, FIG. 1D is an
enlarged view of the device region 120 in the multi-device package.
As shown in FIG. 1D, each of the device regions 120 includes a
semiconductor device 121, an inter-layer dielectric (ILD) layer 124
covering the semiconductor device 121, an inter-metal dielectric
(IMD) layer 126 on the ILD layer 124, and a metal interconnect
structure 128 through the IMD layer 126 and the ILD layer 124 to
electrically connect the semiconductor device 121. In addition, the
device region 120 has a conductive pad 122, which is the uppermost
metal layer of the metal interconnect structure 128. In some
embodiments, the substrate 110 is formed from a wafer including
silicon, germanium, or other III-V group elements, but not limited
thereto. In various embodiments, the semiconductor device 121 is a
memory device, but not limited thereto. Other semiconductor devices
are also suitable in the present disclosure.
[0038] Continuing in FIG. 1C, the first redistribution layer 130 is
disposed on the first surface 112 of the substrate 110 and
electrically connected to at least two device regions 120. The
first redistribution layer 130 is in contact with the conductive
pads 122 of the device regions 120, so as the device regions 120
are electrically connected to each other by the first
redistribution layer 130. Referring back to FIG. 1A, the
multi-device package 100 illustrated in FIG. 1A has four device
regions 120 therein, and the first redistribution layer 130
electrically connects these four device regions 120. For example,
the semiconductor device 121 may be a memory device, and each of
the device regions 120 provides a storage capacity of 2 gigabytes.
The first redistribution 130 integrates these four device regions
120 to achieve a storage capacity of 8 gigabytes, but not limited
thereto.
[0039] Furthermore, the first redistribution layer 130 is applied
to redistribute or relocate the signals to an arrangement of
external devices or input/output connections. The first
redistribution layer 130 includes a dielectric layer 132, a
plurality of metal layers 134 and a plurality of vias 136. These
metal layers 134 are arranged in parallel inside the dielectric
layer 132, and the vias 136 are also in the dielectric layer 132,
which the two adjacent metal layers 134 are electrically connected
by the via 136. To be noticed, the metal layers 134 are
electrically connected to the conductive pads 122 of the device
regions 120 by the vias 136, so as to electrically connect at least
two device regions 120 through the conductive pads 122, the vias
136 and the metal layers 134. In addition, the number of the metal
layers 136 is predetermined according to design requirement. In
some embodiments, the vias 136 and the metal layers 134 are formed
of aluminum, copper, or a combination thereof, but not limited
thereto. Other conductive materials are also suitable for the vias
136 and the metal layers 134. In various embodiments, the
dielectric layer 132 is formed of silicon oxide, silicon nitride,
silicon oxynitride, or a combination thereof, but not limited
thereto. Other insulating materials are also suitable for the
dielectric layer 132.
[0040] Continuing in FIGS. 1A and 1C, the external chip 140 is
disposed on the first redistribution layer 130, and a plurality of
first connectors 150 are interposed between the first
redistribution layer 130 and the external chip 140 to interconnect
the two. As aforementioned, the first redistribution layer 130 is
electrically connected to at least two device regions 120, and the
first connectors 150 are disposed on and in contact with the first
redistribution layer 130. The external chip 140 is disposed on and
in contact with the first connectors 150, so that the external
device 140 is electrically connected to the device regions 120 via
the first connectors 150, the first redistribution layer 130 and
the conductive pads 122. Therefore, the external chip 140 is able
to receive the signals from the device regions 120 to perform
computing operation.
[0041] In some embodiments, the multi-device package 100 further
includes a molding layer 170 covering the first redistribution
layer 130 and the external chip 140, so as to protect the external
chip 140 and prevent warpage of the multi-device package 100. In
various embodiments, the molding layer 170 may include epoxy.
[0042] Continuing in FIG. 1C, a conductive contact 116 is extended
from the second surface 114 to the first surface 112 of the
substrate 110 to electrically connect the device region 120.
Specifically, the conductive contact 116 is in contact with the
conductive pad 122 of the device region 120. Referring to FIG. 1D
at the same time, the conductive contact 116 passes the ILD layer
124 and the IMD layer 126 to contact the conductive pad 122. To be
noticed, the conductive contact 116 is not in contact with the
semiconductor device 121 in the device region 120 to avoid
connection errors. In some embodiments, the conductive contact 116
is in contact with one of the metal layer of the metal interconnect
structure 128.
[0043] Continuing in FIGS. 1B and 10, a plurality of second
connectors 160 are disposed below the second surface 114 of the
substrate 110, and each of the second connectors 160 is in contact
with the conductive contact 116, so that the computing results
generated by the external chip 140 is transmitted to the second
connectors 160 by the first connectors 150, the first
redistribution layer 130, the conductive pad 112 and the conductive
contact 116. These second connectors 160 further transmit the
computing results to other external devices, such as a printed
circuit board. In some embodiments, a diameter of the second
connector 160 is larger than a diameter of the first connector 150.
In some embodiments, the first connectors 150 and the second
connectors 160 may be solder bumps or solder balls formed of tin,
but not limited thereto.
[0044] Referring to FIG. 2A, FIG. 2B and FIG. 20 at the same time.
FIG. 2A is a top view of a multi-device package according to
various embodiments of the present disclosure, FIG. 2B is a bottom
view of a multi-device package according to various embodiments of
the present disclosure, and FIG. 20 is a cross-sectional view of
the multi-device package in FIGS. 2A and 2B along the line AA,
according to various embodiments of the present disclosure. As
shown in FIG. 20, the difference between the multi-device package
100 and the multi-device package 200 is that the multi-device
package 200 further includes a second redistribution layer 270
below the second surface 114, and the second connectors 160 is
disposed below and in contact with the second redistribution layer
270.
[0045] The second redistribution layer 270 includes a dielectric
layer 272, a plurality of metal layers 274 and a plurality of vias
276. These metal layers 274 are arranged in parallel inside the
dielectric layer 272, and the vias 276 are also in the dielectric
layer 272, which the two adjacent metal layers 274 are electrically
connected by the via 276. To be noticed, the metal layers 274 are
also electrically connected to the conductive contact 116 by the
vias 276. In addition, the number of the metal layers 274 is
predetermined according to design requirement. As aforementioned,
the second connectors 160 are in contact with the second
redistribution layer 270, so that the computing results generated
by the external chip 140 is transmitted to the second connectors
160 via the first connectors 150, the first redistribution layer
130, the conductive pad 122, the conductive contact 116 and the
second redistribution layer 270. These second connectors 160
further transmit the computing results to other external devices,
such as a printed circuit board. Most importantly, layout of the
second connectors 160 is more flexible due to the formation of the
second redistribution layer 270.
[0046] Comparing FIG. 1C and FIG. 2C, a density of the second
connectors 160 below the second surface 114 in the multi-device
package 200 is larger than a density of the second connectors 160
below the second surface 114 in the multi-device package 100.
Specifically, each of the second connectors 160 in the multi-device
package 100 is corresponded to one conductive contact 116.
Relatively, the redistribution layer 270 in the multi-device
package 200 redistributes electrical paths, and thus enlarges the
space for placing the second connectors 160 to increases its
density. Therefore, the electrical connection between the
multi-device package 200 and the printed circuit board is enhanced
due to the higher density of the second connectors 160.
[0047] Refer to FIGS. 3A to 3E to further clarify a process of
manufacturing the multi-device package 100 shown in FIG. 1A to 1C.
FIGS. 3A to 3E are cross-sectional views of the multi-device
package in FIG. 1C at an intermediate stage of fabrication, in
accordance with various embodiments.
[0048] Referring to FIG. 3A, a wafer 300 having a first surface 112
and a second surface 114 opposite to the first surface 112 is
provided, which the wafer 300 has at least two device regions 120
therein. Then, a first redistribution layer 130 is formed on the
first surface 112, which the first redistribution layer 130 is
electrically connected to the two device regions 120. As
aforementioned in FIG. 1D, each of the device regions 120 includes
a semiconductor device 121, an inter-layer dielectric (ILD) layer
124 covering the semiconductor device 121, an inter-metal
dielectric (IMD) layer 126 on the ILD layer 124, and a metal
interconnect structure 128 through the IMD layer 126 and the ILD
layer 124 to electrically connect the semiconductor device 121. In
addition, each of the device region 120 has a conductive pad 122,
which is the uppermost metal layer of the metal interconnect
structure 128. The first redistribution layer 130 is formed by
following steps. First, a dielectric material is deposited to cover
the first surface 112, and a photolithography etching process is
performed to remove a portion of the dielectric material.
Therefore, openings are formed to expose the device regions 120 of
the wafer 300. Specifically, each of the openings is corresponded
to one conductive pad 122 of the device regions 120. Then, vias 136
are respectively formed in these openings, and a metal layer 134 is
formed on the vias 136. The metal layer 134 is patterned according
to layout design, so as to electrically connect at least two device
regions 120. The steps mentioned above are repeated few times to
obtain the first redistribution layer 130 having a plurality of
metal layers 136 inside a dielectric layer 132, and the number of
the metal layers 136 is predetermined according to design
requirement.
[0049] Referring to FIG. 3B, a plurality of first connectors 150 is
formed on the first redistribution layer 130, and an external chip
140 is mounted on the first connectors 150. A reflow process is
performed to form these first connectors 150 on the first
redistribution layer 130, and the external chip 140 is formed to
contact the first connectors 150. Thus, the external device 140 is
electrically connected to the device regions 120 via the first
connectors 150, the first redistribution layer 130 and the
conductive pads 122, so the external chip 140 is able to receive
the signals from the device regions 120 to perform computing
operation. In addition, a molding layer 170 is further formed to
cover the first redistribution layer 130 and the external chip 140,
so as to protect the external chip 140 and prevent warpage of the
wafer 300. In various embodiments, the molding layer 170 may
include epoxy.
[0050] Continuing in FIG. 3C, a temporary adhesive layer 310 is
formed on the molding layer 170, and the wafer 300 is thinned to
reduce its thickness, so as to decrease the size of the subsequent
multi-device package. The temporary adhesive layer 310 includes a
carrier 314 and an adhesive layer 312, which the temporary adhesive
layer 310 reduces the stress from the thinning process. Therefore,
risk of wafer fracture is decreased. In some embodiments, the
temporary adhesive layer 310 is a tape. In some embodiments, the
wafer 300 is thinned by a chemical mechanical polishing
process.
[0051] Continuing in FIG. 3D, a conductive contact 116 is formed to
extend from the second surface 114 to the first surface 112, and
the conductive contact 116 is electrically connected to the device
region 120. Specifically, a portion of the wafer 300 is removed to
form a through hole extending from the second surface 114 to the
first surface 112, which the conductive pad 122 is exposed in the
through hole. Then, a conductive material is filled in the through
hole to form the conductive contact 116 electrically connecting to
the conductive pad 122. In some embodiments, the portion of the
wafer 300 is removed by a photolithography etching process to form
the through hole. In various embodiments, the conductive contact
116 are formed of copper, aluminum, or a combination thereof, but
not limited thereto. After forming the conductive contact 116, the
temporary adhesive layer 310 is removed. A suitable solvent is
applied to eliminate the adhesive property of the adhesive layer
312 to separate temporary adhesive layer 310 from the wafer 300. In
some embodiments, the temporary adhesive layer 310 is removed
before forming the conductive contact 116.
[0052] Referring to FIG. 3E, a plurality of second connectors 160
are formed below the second surface 114, and the wafer 300 is diced
along a scribe line 320 to form the multi-device package shown 100
in FIG. 2A to 2C. A reflow process is performed to form these
second connectors 160 below the second surface, and each of the
second connectors 160 is in contact with one conductive contact
116. Then, the wafer 300 is diced along the scribe line 320 to form
individual multi-device packages 100. To be noticed, the scribe
line 320 does not pass the metal layers 134 of the first
redistribution layer 130 to avoid the line disconnection of the
first redistribution layer 130. In various embodiments, the
multi-device package 100 is further connected to the printed
circuit board by the second connectors 160, and the computing
results generated by the external chip 140 is transmitted to the
printed circuit board via the first connectors 150, the first
redistribution layer 130, the conductive contact 116 and the second
connectors 160.
[0053] Please refer to FIGS. 4A to 4F to further clarify another
process of manufacturing the multi-device package 200 shown in
FIGS. 2A to 2C. FIGS. 4A to 4F are cross-sectional views of the
multi-device package in FIGS. 2A to 20 at an intermediate stage of
fabrication, in accordance with various embodiments.
[0054] Referring to FIG. 4A, a wafer 400 having a first surface 112
and a second surface 114 opposite to the first surface 112 is
provided, which the wafer 400 has at least two device regions 120
therein. Then, a first redistribution layer 130 is formed on the
first surface 112, which the first redistribution layer 130 is
electrically connected to the two device regions 120. As
aforementioned in FIG. 1D, each of the device regions 120 includes
a semiconductor device 121, an inter-layer dielectric (ILD) layer
124 covering the semiconductor device 121, an inter-metal
dielectric (IMD) layer 126 on the ILD layer 124, and a metal
interconnect structure 128 through the IMD layer 126 and the ILD
layer 124 to electrically connect the semiconductor device 121. In
addition, each of the device region 120 has a conductive pad 122,
which is the uppermost metal layer of the metal interconnect
structure 128. The steps of forming the first redistribution layer
230 is described in FIG. 3A, and the details are not described
herein.
[0055] Referring to FIG. 4B, a plurality of first connectors 150 is
formed on the first redistribution layer 130, and an external chip
140 is mounted on the first connectors 150. A reflow process is
performed to form these first connectors 150 on the first
redistribution layer 130, and the external chip 140 is formed to
contact the first connectors 150. Thus, the external device 140 is
electrically connected to the device regions 120 via the first
connectors 150, the first redistribution layer 130 and the
conductive pads 122, so the external chip 140 is able to receive
the signals from the device regions 120 to perform computing
operation. In addition, a molding layer 170 is further formed to
cover the first redistribution layer 130 and the external chip 140,
so as to protect the external chip 140 and prevent warpage of the
wafer 400. In various embodiments, the molding layer 170 may
include epoxy.
[0056] Continuing in FIG. 4C, a temporary adhesive layer 310 is
formed on the molding layer 170, and the wafer 400 is thinned to
reduce its thickness, so as to decrease the size of the subsequent
multi-device package. The temporary adhesive layer 310 includes a
carrier 314 and an adhesive layer 312, which the temporary adhesive
layer 310 reduces the stress from the thinning process. Therefore,
risk of wafer fracture is decreased. In some embodiments, the
temporary adhesive layer 310 is a tape. In some embodiments, the
wafer 400 is thinned by a chemical mechanical polishing
process.
[0057] Referring to FIG. 4D, a conductive contact 116 is formed to
extend from the second surface 114 to the first surface 112, and
the conductive contact 116 is electrically connected to the device
region 120. The steps of forming the conductive contact 116 is
described in FIG. 3D, and the details are not described herein.
After forming the conductive contact 116, the temporary adhesive
layer 310 is removed. A suitable solvent is applied to eliminate
the adhesive property of the adhesive layer 312 to separate
temporary adhesive layer 310 from the wafer 400. In some
embodiments, the temporary adhesive layer 310 is removed before
forming the conductive contact 116.
[0058] Referring to FIG. 4E, a second redistribution layer 270 is
formed below the second surface 114. The second redistribution
layer 270 is formed by following steps. First, a dielectric
material is deposited to cover the second surface 114, and a
photolithography etching process is performed to remove a portion
of the dielectric material. Therefore, openings are formed, and
each of the openings is corresponded to the conductive contact 116.
Then, vias 276 are respectively formed in these openings, and a
metal layer 274 is formed below the vias 276. The metal layer 274
is further patterned according to layout design. The steps
mentioned above are repeated few times to obtain the second
redistribution layer 270 having a plurality of metal layers 274
inside a dielectric layer 272, and the number of the metal layers
274 is predetermined according to design requirement.
[0059] Continuing in FIG. 4F, a plurality of second connectors 160
is formed below the second redistribution layer 270, and the wafer
400 is diced along a scribe line 420 to form the multi-device
package 200 shown in FIGS. 2A to 2C. A reflow process is performed
to form these second connectors 160 below the second redistribution
layer 270, and each of the second connectors 160 is in contact with
the metal layer 274 of the second redistribution layer 270. Then,
the wafer 400 is diced along the scribe line 420 to form individual
multi-device packages 200. To be noticed, the scribe line 420 does
not pass the metal layers 134 of the first redistribution layer 130
and the metal layers 274 of the second redistribution layer 270 to
avoid the line disconnection. In various embodiments, the
multi-device package 200 is further connected to the printed
circuit board by the second connectors 160, and the computing
results generated by the external chip 140 is transmitted to the
printed circuit board via the first connectors 150, the first
redistribution layer 130, the conductive contact 116, the second
redistribution layer 270 and the second connectors 160.
[0060] The embodiments of the present disclosure discussed above
have advantages over existing package and processes, and the
advantages are summarized below. The present disclosure provides a
wafer-level packaging process, which is applied to integrate at
least two device regions in one multi-device package without using
a carrier substrate, and therefore the substrate and the device
regions of the multi-device package have no interface therebetween.
Furthermore, the device regions in the wafer are integrated
directly, so as to decrease risk of disconnection and fracture in
the device regions. Summarize above points, the costs of the
multi-device package is decreased due to a omission of the carrier
substrate, and the efficiency of the packaging process is increased
to enhance the yield of the multi-device package.
[0061] Although the present invention has been described in
considerable detail with reference to certain embodiments thereof,
other embodiments are possible. Therefore, the spirit and scope of
the appended claims should not be limited to the description of the
embodiments contained herein.
[0062] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
present invention without departing from the scope or spirit of the
invention. In view of the foregoing, it is intended that the
present invention cover modifications and variations of this
invention provided they fall within the scope of the following
claims.
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