U.S. patent application number 15/199413 was filed with the patent office on 2016-12-01 for method for fabricating semiconductor device.
The applicant listed for this patent is Nanya Technology Corp.. Invention is credited to Jei-Cheng Huang, Hai-Han Hung, Hsiu-Chun Lee, Wei-Ming Liao, Shin-Yu Nieh, Tieh-Chiang Wu.
Application Number | 20160351678 15/199413 |
Document ID | / |
Family ID | 51523762 |
Filed Date | 2016-12-01 |
United States Patent
Application |
20160351678 |
Kind Code |
A1 |
Nieh; Shin-Yu ; et
al. |
December 1, 2016 |
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
Abstract
The invention provides a method for fabricating a semiconductor
device, including: forming a dummy gate on a substrate, forming an
inter-layer dielectric layer (ILD) on the dummy gate and the
substrate, forming a metal layer on the upper surface of the dummy
gate, removing the dummy gate to form a trench in the inter-layer
dielectric layer (ILD), conformally forming a gate dielectric layer
in the trench, conformally forming a first conductive type metal
layer on the gate dielectric layer, anisotropic etching the first
conductive type metal layer and the gate dielectric layer over the
metal layer to form a gap in the inter-layer dielectric layer
(ILD), and filling a second conductive type metal layer in the
gap.
Inventors: |
Nieh; Shin-Yu; (Taoyuan,
TW) ; Wu; Tieh-Chiang; (Taoyuan, TW) ; Liao;
Wei-Ming; (Taoyuan, TW) ; Huang; Jei-Cheng;
(Taoyuan, TW) ; Hung; Hai-Han; (Taoyuan, TW)
; Lee; Hsiu-Chun; (Taoyuan, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Nanya Technology Corp. |
Taoyuan |
|
TW |
|
|
Family ID: |
51523762 |
Appl. No.: |
15/199413 |
Filed: |
June 30, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13846169 |
Mar 18, 2013 |
|
|
|
15199413 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/28079 20130101;
H01L 29/517 20130101; H01L 29/518 20130101; H01L 29/66553 20130101;
H01L 29/66545 20130101; H01L 29/4958 20130101; H01L 21/28088
20130101; H01L 21/28105 20130101; H01L 29/4983 20130101; H01L
29/4966 20130101; H01L 29/495 20130101 |
International
Class: |
H01L 29/49 20060101
H01L029/49; H01L 29/66 20060101 H01L029/66; H01L 29/51 20060101
H01L029/51; H01L 21/28 20060101 H01L021/28 |
Claims
1. A method for fabricating a semiconductor device, comprising:
providing a substrate; forming a dummy gate on the substrate;
forming an inter-layer dielectric layer (ILD) on the dummy gate and
the substrate; performing a first chemical mechanical polishing
(CMP) process to the inter-layer dielectric layer (ILD) to expose
an upper surface of the dummy gate; forming a metal layer on the
upper surface of the dummy gate; removing the dummy gate to form a
trench in the inter-layer dielectric layer (ILD); conformally
forming a gate dielectric layer in the trench; conformally forming
a first conductive type metal layer on the gate dielectric layer;
anisotropic etching the first conductive type metal layer and the
gate dielectric layer over the metal layer to form a gap in the
inter-layer dielectric layer (ILD) and to expose a portion of the
gate dielectric layer, wherein the first conductive type metal
layer is divided into two first conductive type metal layers
defining the gap; filling a second conductive type metal layer in
the gap, wherein the second conductive type metal layer is
sandwiched between the two first conductive type metal layers to
form a dual work function metal gate layer, wherein the two first
conductive type metal layers are n+ metal layers and the second
conductive type metal layer is a p+ metal layer, and wherein the
first conductive type metal layer and the second conductive type
metal layer both directly contact the gate dielectric layer; and
performing a second chemical mechanical polishing (CMP) process to
the second conductive type metal layer and the metal layer to
expose an upper surface of the dual work function metal gate
layer.
2. The method for fabricating a semiconductor device as claimed in
claim 1, before forming the inter-layer dielectric layer (ILD) on
the dummy gate and the substrate, further comprising: forming a
spacer on a sidewall of the dummy gate.
3. The method for fabricating a semiconductor device as claimed in
claim 1, wherein the metal layer comprises p+ metal layer or n+
metal layer.
4. The method for fabricating a semiconductor device as claimed in
claim 1, after removing the first conductive type metal layer and
the gate dielectric layer over the metal layer, wherein the gate
dielectric layer has a U-shaped structure, and the U-shaped gate
dielectric layer comprises a horizontal portion and two vertical
portions, and the two vertical portions are located at opposite
ends of the horizontal portion.
5. The method for fabricating a semiconductor device as claimed in
claim 4, wherein two first conductive type metal layers are
adjacent to the vertical portions of the U-shaped gate dielectric
layer.
6. The method for fabricating a semiconductor device as claimed in
claim 4, wherein the inter-layer dielectric layer (ILD) is further
formed on a sidewall of the U-shaped gate dielectric layer.
7. The method for fabricating a semiconductor device as claimed in
claim 4, wherein the inter-layer dielectric layer (ILD) surrounds
the U-shaped gate dielectric layer.
8. The method for fabricating a semiconductor device as claimed in
claim 4, further comprising: forming a spacer on the substrate,
wherein the spacer is formed between the inter-layer dielectric
layer (ILD) and the U-shaped gate dielectric layer.
9. The method for fabricating a semiconductor device as claimed in
claim 1, wherein the n+ metal layer has a work function of about
4.1-4.9.
10. The method for fabricating a semiconductor device as claimed in
claim 1, wherein the n+ metal layer comprises scandium (Sc),
zirconium (Zr), hafnium (Hf), aluminum (Al), titanium, (Ti),
tantalum (Ta) or niobium (Nb).
11. The method for fabricating a semiconductor device as claimed in
claim 1, wherein the p+ metal layer has a work function of about
4.7-5.0.
12. The method for fabricating a semiconductor device as claimed in
claim 1, wherein the p+ metal layer comprises tungsten (W),
platinum (Pt), ruthenium (Ru), molybdenum (Mo), titanium carbide
(TiC), zirconium arbide (ZrC), tantalum carbide (TaC), tungsten
carbide (WC), titanium nitride (TiN), tantalum nitride (TaN) or
ruthenium oxide (RuO).
13. The method for fabricating a semiconductor device as claimed in
claim 1, wherein the gate dielectric layer comprises high-k
dielectric material.
14. The method for fabricating a semiconductor device as claimed in
claim 13, wherein the high-k dielectric material comprises
HfO.sub.2, ZrO.sub.2, TiO.sub.2, Al.sub.2O.sub.3, HfSiO, HfSiON,
HfTaO, HfTiO, HfZrO or combinations thereof.
15. The method for fabricating a semiconductor device as claimed in
claim 1, wherein a width of the trench is larger than that of the
gap.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a Divisional of pending U.S. patent
application Ser. No. 13/846,169, filed Mar. 18, 2013 and entitled
"SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME," which
is hereby incorporated by reference.
BACKGROUND OF THE DISCLOSURE
[0002] Field of the Disclosure
[0003] The present disclosure relates to a semiconductor device,
and in particular relates to a semiconductor device having a dual
work function metal gate and method for fabricating the same.
[0004] Description of the Related Art
[0005] In the course of the semiconductor integrated circuit (IC)
evolution, functional density (i.e., the number of interconnected
devices per chip area) has generally increased while geometry size
(i.e., the component (or line) that can be created using a
fabrication process) has decreased.
[0006] Specifically, as the dimension of the complementary
metal-oxide-semiconductor (CMOS) devices decreases, short channel
effect is increased. Thus, the threshold voltage (V.sub.th) of CMOS
devices is undesirably reduced.
[0007] There are several methods to increase the threshold voltage
(V.sub.th), such as more channel doping, S/D doping reduction,
increase halo implants, etc. However, the conventional methods have
some drawbacks, for example, junction leakage is increased, drain
current saturation (IDs) is increased, and junction capacitance is
high.
[0008] Mid-gap materials having a work function of about 4.6 eV
(such as TiN, Ta, W) (near the mid-gap of silicon) may be used as
the gate. However, the undesirably gate-induced drain leakage
(GIDL) still exists.
[0009] Therefore, there is a need to develop a semiconductor device
having a high threshold voltage (V.sub.th) and a low gate-induced
drain leakage (GIDL).
BRIEF SUMMARY OF THE DISCLOSURE
[0010] The invention provides a semiconductor device, comprising: a
substrate; a U-shaped gate dielectric layer formed on the
substrate; and a dual work function metal gate layer on the inner
surface of U-shaped gate dielectric layer, wherein the dual work
function metal gate layer comprises a first conductive type metal
layer and a second conductive type metal layer.
[0011] The invention also provides a method for fabricating a
semiconductor device, comprising: providing a substrate; forming a
dummy gate on the substrate; forming an inter-layer dielectric
layer (ILD) on the dummy gate and the substrate; performing a first
chemical mechanical polishing (CMP) process to the inter-layer
dielectric layer (ILD) to expose an upper surface of the dummy
gate; forming a metal layer on the upper surface of the dummy gate;
removing the dummy gate to form a trench in the inter-layer
dielectric layer (ILD); conformally forming a gate dielectric layer
in the trench; conformally forming a first conductive type metal
layer on the gate dielectric layer; removing the first conductive
type metal layer and the gate dielectric layer over the metal layer
to form a gap in the inter-layer dielectric layer (ILD) and to
expose a portion of the gate dielectric layer; filling a second
conductive type metal layer in the gap, wherein the second
conductive type metal layer is sandwiched between two first
conductive type metal layers to form a dual work function metal
gate layer; and performing a second chemical mechanical polishing
(CMP) process to the second conductive type metal layer and the
metal layer to expose an upper surface of the dual work function
metal gate layer.
[0012] A detailed description is given in the following embodiments
with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWING
[0013] For a more complete understanding of the present disclosure,
and the advantages thereof, reference is now made to the following
descriptions taken in conjunction with the accompanying drawings,
in which:
[0014] FIGS. 1A-1H and 1H' show cross-sectional schematic
representations of various stages of fabricating a semiconductor
device in accordance with an embodiment of the invention.
DETAILED DESCRIPTION OF THE DISCLOSURE
[0015] The following description is of the best-contemplated mode
of carrying out the disclosure. This description is made for the
purpose of illustrating the general principles of the disclosure
and should not be taken in a limiting sense. The scope of the
disclosure is best determined by reference to the appended
claims.
[0016] The invention provides a semiconductor device having a dual
work function metal gate structure.
[0017] FIGS. 1A-1H and 1H' show cross-sectional schematic
representations of various stages of fabricating a semiconductor
device 100 in accordance with an embodiment of the invention.
[0018] Referring to FIG. 1A, a substrate 102 is provided, such as a
silicon substrate. The substrate 102 may alternatively include
silicon germanium, gallium arsenic, or other suitable semiconductor
materials. The substrate 102 may further include other features
such as various doped regions, a buried layer, and/or an epitaxy
layer. Furthermore, the substrate 102 may be a semiconductor on
insulator such as silicon on insulator (SOI). In other embodiments,
the semiconductor substrate 102 may include a doped epi layer, a
gradient semiconductor layer, and/or may further include a
semiconductor layer overlying another semiconductor layer of a
different type such as a silicon layer on a silicon germanium
layer. In other examples, a compound semiconductor substrate may
include a multilayer silicon structure or a silicon substrate may
include a multilayer compound semiconductor structure.
[0019] Additionally, an isolation structure (not shown) such as a
shallow trench isolation (STI) feature, may be formed in the
substrate 102 for isolating an active region in the substrate, as
is known in the art. The isolation structure may be formed of
silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped
silicate (FSG), and/or a low k dielectric material known in the
art.
[0020] Then, a dummy gate 104 is formed on the substrate 102. The
dummy gate 104 may comprise a doped or undoped poly-crystalline
silicon (or amorphous silicon), a metal (e.g., tantalum, titanium,
molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a
metal silicide (e.g., titanium silicide, cobalt silicide, nickel
silicide, tantalum silicide), a metal nitride (e.g., titanium
nitride, tantalum nitride), other conductive materials or
combinations thereof. In an embodiment, the dummy gate 104 is
poly-silicon and may be formed by low-pressure chemical vapor
deposition.
[0021] Next, an inter-layer dielectric layer (ILD layer) 108 is
formed on the substrate 102 and the dummy gate 104. The inter-layer
dielectric layer 108 may be formed by atomic layer deposition
(ALD), physical vapor deposition (PVD), chemical vapor deposition
(CVD), or other acceptable methods for forming an ILD layer 108.
The inter-layer dielectric layer 108 may comprise doped or undoped
silicon oxide, although other materials such as silicon nitride
doped silicate glass, high-k materials, combinations of these, or
the like, may alternatively be utilized.
[0022] Additionally, before forming the inter-layer dielectric
layer 108, the spacers 106 may be formed on the substrate 102 and a
sidewall of the dummy gate 104. The spacers 106 may be formed by
blanket depositing one or more spacer layers (not shown) on the
dummy gate 104 and the substrate 102. The spacers 106 may comprise
SiN, oxynitride, SiC, SiON, oxide, and the like and may be formed
by commonly used methods such as chemical vapor deposition (CVD),
plasma enhanced CVD, sputter, and other methods known in the art.
Note that in another embodiment, the spacers may not be formed.
[0023] The source/drain regions (not shown in FIG. 1A) may be
formed within the substrate 102 on opposing sides of the dummy gate
104. Thus, the source/drain regions may be formed so as to define a
channel region located beneath the dummy gate 104.
[0024] Referring to FIG. 1A again, a first chemical mechanical
polishing (CMP) is performed to the inter-layer dielectric layer
(ILD) 108 to expose an upper surface 104a of the dummy gate
104.
[0025] Referring to FIG. 1B, a metal layer 110 is formed on the
upper surface 104a of the dummy gate 104. The metal layer 110 may
be a p.sup.+ metal layer or n.sup.+ metal layer. The metal layer
110 may be formed by atomic layer deposition (ALD), physical vapor
deposition (PVD), chemical vapor deposition (CVD), or other
acceptable methods.
[0026] In one embodiment, when the semiconductor device is an PMOS
device, the metal layer 110 is an n.sup.+ metal layer. In another
embodiment, when the semiconductor device is NMOS device, the metal
layer 110 is a p.sup.+ metal layer.
[0027] Referring to FIG. 1C, the dummy gate 104 is removed to form
a trench 120 in the inter-layer dielectric layer 108, and the
trench 120 has a depth of D1.
[0028] Referring to FIG. 1D, a gate dielectric layer 122 is
conformally formed in the trench 120. The gate dielectric layer 122
may be formed by atomic layer deposition (ALD), chemical vapor
deposition (CVD), or other acceptable methods. The gate dielectric
layer 122 has a thickness of about 5-70 .ANG., preferably about
5-50 .ANG..
[0029] Additionally, the gate dielectric layer 122 comprises high-k
dielectric material, such as HfO.sub.2, ZrO.sub.2, TiO.sub.2,
Al.sub.2O.sub.3, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or combinations
thereof.
[0030] Referring to FIG. 1E, a first conductive type metal layer
124 is conformally formed on the gate dielectric layer 122. The
first conductive type metal layer 124 may be formed by atomic layer
deposition (ALD), chemical vapor deposition (CVD), or other
acceptable methods. The first conductive type metal layer 124 has a
thickness of about 4-20 nm, preferably about 4-10 nm.
[0031] In one embodiment, when the semiconductor device is a PMOS
device, the first conductive type metal layer 124 is an n.sup.+
metal layer.
[0032] In another embodiment, when the semiconductor device is NMOS
device, the first conductive type metal layer 124 is a p.sup.+
metal layer.
[0033] The n.sup.+ metal layer has a work function of about 4.1-4.9
and comprises scandium (Sc), zirconium (Zr), hafnium (Hf), aluminum
(Al), titanium, (Ti), tantalum (Ta) or niobium (Nb).
[0034] The p.sup.+ metal layer has a work function of about 4.7-5.0
and comprises tungsten (W), platinum (Pt), ruthenium (Ru),
molybdenum (Mo), titanium carbide (TiC), zirconium arbide (ZrC),
tantalum carbide (TaC), tungsten carbide (WC), titanium nitride
(TiN), tantalum nitride (TaN) or ruthenium oxide (RuO).
[0035] Referring to FIG. 1E, the first conductive type metal layer
124 and the gate dielectric layer 122 over the metal layer 110 is
removed to form a gap 125 in the inter-layer dielectric layer 108
and to expose a portion of the gate dielectric layer 122.
[0036] Note that after the above removing step, the gate dielectric
layer 122 has a U-shaped structure, and the U-shaped gate
dielectric layer 122 comprises a horizontal portion 122a and two
vertical portions 122b, and the two vertical portions 122b are
located at opposite ends of the horizontal portion 122a. Two first
conductive type metal layers 124 are adjacent to the vertical
portions 122b of the U-shaped gate dielectric layer 122.
[0037] An etching process such as a dry etching technique (e.g.,
anisotropic etching) may be performed on the first conductivity
type metal layer 124 such that a portion of the first conductivity
type metal layer 124 remains on the sidewalls of horizontal portion
122a of the U-shaped gate dielectric layer 122.
[0038] The gap 125 has a width of D2, and the D1 of the trench 120
is larger than D2 of the gap 125.
[0039] Referring to FIG. 1G, a second conductive type metal layer
126 is filled in the gap 125, and thus the second conductive type
metal layer 126 is sandwiched between two first conductive type
metal layers 124 to form a dual work function metal gate layer
130.
[0040] In one embodiment, when the semiconductor device is a PMOS
device, the first conductive type metal layer 124 is an n.sup.+
metal layer, and the second conductive type metal layer 126 is a
p.sup.+ metal layer.
[0041] In another embodiment, when the semiconductor device is an
NMOS device, the first conductive type metal layer 124 is a p.sup.+
metal layer, and the second conductive type metal layer 126 is an
n.sup.+ metal layer.
[0042] Referring to FIG. 1H, a second chemical mechanical polishing
(CMP) is performed to the second conductive type metal layer 126
and the metal layer 110 to expose an upper surface of the dual work
function metal gate layer 130. Thus, a semiconductor device 100
having the dual work function metal gate layer 130 is formed by the
above-mentioned steps.
[0043] As shown in FIG. 1H, the invention also provides a
semiconductor device 100 which comprises: a substrate 102; a
U-shaped gate dielectric layer 122 formed on the substrate 102; and
a dual work function metal gate layer 130 on the inner surface of
U-shaped gate dielectric layer 122, wherein the dual work function
metal gate layer 130 comprises a first conductive type metal layer
124 and a second conductive type metal layer 126. In another
embodiment, the invention also provides a semiconductor device
100', as shown in FIG. 1H'. The semiconductor device 100' shown in
FIG. 1H' is similar to the semiconductor device 100 shown in FIG.
1H, except that the semiconductor device 100' does not comprise the
spacers. As shown in FIG. 1H', the inter-layer dielectric layer 108
is formed on the sidewalls of the U-shaped gate dielectric layer
122.
[0044] The U-shaped gate dielectric layer 122 comprises a
horizontal portion 122a and two vertical portions 122b, and the two
vertical portions 122b are located at opposite ends of the
horizontal portion 122a. Additionally, the dual work function metal
gate layer 130 comprises two first conductive type metal layers 124
adjacent to the vertical portions 122b of the U-shaped gate
dielectric layer 122 and the second conductive type metal layer 126
sandwiched between two first conductive type metal layers 124.
[0045] For example, when the semiconductor device is a PMOS device,
the first conductive type metal layer 124 is an n.sup.+ metal
layer, and the second conductive type metal layer 126 is a p.sup.+
metal layer. In other words, the p.sup.+ metal layer sandwiched
between two n.sup.+ metal layers. Because the middle p.sup.+ metal
layer has a higher work function, the dual work function metal gate
layer 130 has a higher threshold voltage (V.sub.th) for the
p-channel below the middle p.sup.+ metal layer. Because the n+
metal layer has a lower work function, the undesirably gate-induced
drain leakage (GIDL) between the n+ metal layer and the drain (not
shown in figures) is reduced.
[0046] From the above description, compared with the single work
function metal gate in prior art, due to the dual work function
metal gate layer of the invention having two different work
functions, the threshold voltage (Vth) is increased and the
gate-induced drain leakage (GIDL) is reduced.
[0047] While the disclosure has been described by way of example
and in terms of the preferred embodiments, it is to be understood
that the disclosure is not limited to the disclosed embodiments. To
the contrary, it is intended to cover various modifications and
similar arrangements (as would be apparent to those skilled in the
art). Therefore, the scope of the appended claims should be
accorded the broadest interpretation so as to encompass all such
modifications and similar arrangements.
* * * * *