loadpatents
name:-0.010826110839844
name:-0.010495901107788
name:-0.00050806999206543
Zuchowski; Paul Steven Patent Filings

Zuchowski; Paul Steven

Patent Applications and Registrations

Patent applications and USPTO patent grants for Zuchowski; Paul Steven.The latest application filed is for "methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applications".

Company Profile
0.9.8
  • Zuchowski; Paul Steven - Jericho VT
  • Zuchowski; Paul Steven - Cambridge VT
  • Zuchowski; Paul Steven - Fletcher VT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
Grant 7,696,811 - Barrows , et al. April 13, 2
2010-04-13
Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
Grant 7,671,666 - Barrows , et al. March 2, 2
2010-03-02
Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
Grant 7,459,958 - Barrows , et al. December 2, 2
2008-12-02
Methods To Reduce Threshold Voltage Tolerance And Skew In Multi-threshold Voltage Applications
App 20080265983 - Barrows; Corey Kenneth ;   et al.
2008-10-30
Methods And Circuits To Reduce Threshold Voltage Tolerance And Skew In Multi-threshold Voltage Applications
App 20080246533 - Barrows; Corey Kenneth ;   et al.
2008-10-09
Methods And Circuits To Reduce Threshold Voltage Tolerance and Skew In Multi-Threshold Voltage Applications
App 20080122524 - Barrows; Corey Kenneth ;   et al.
2008-05-29
Methods And Circuits To Reduce Threshold Voltage Tolerance And Skew In Multi-threshold Voltage Applications
App 20080086706 - Barrows; Corey Kenneth ;   et al.
2008-04-10
Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories
Grant 6,993,692 - Ouellette , et al. January 31, 2
2006-01-31
Method, System And Apparatus For Aggregating Failures Across Multiple Memories And Applying A Common Defect Repair Solution To All Of The Multiple Memories
App 20040268198 - Ouellette, Michael R. ;   et al.
2004-12-30
System and method for analyzing power distribution using static timing analysis
Grant 6,832,361 - Cohn , et al. December 14, 2
2004-12-14
Global voltage buffer for voltage islands
Grant 6,731,154 - Bednar , et al. May 4, 2
2004-05-04
Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design
Grant 6,651,230 - Cohn , et al. November 18, 2
2003-11-18
Global voltage buffer for voltage islands
App 20030206051 - Bednar, Thomas Richard ;   et al.
2003-11-06
Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design
App 20030110462 - Cohn, John Maxwell ;   et al.
2003-06-12
System and method for analyzing power distribution using static timing analysis
App 20020174409 - Cohn, John Maxwell ;   et al.
2002-11-21
Three dimensional track-based parasitic extraction
Grant 6,185,722 - Darden , et al. February 6, 2
2001-02-06
Redundant vias
Grant 6,026,224 - Darden , et al. February 15, 2
2000-02-15

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