| Patent | Date |
|---|
Generation and delivery of signals in a two-level, multithreaded system
Grant 5,991,790 - Shah , et al. November 23, 1 | 1999-11-23 |
Coprocessor instruction format
Grant 5,021,991 - MacGregor , et al. June 4, 1 | 1991-06-04 |
Coprocessor instruction format
Grant 4,994,961 - MacGregor , et al. February 19, 1 | 1991-02-19 |
Method and apparatus for interrupting a coprocessor
Grant 4,914,578 - MacGregor , et al. April 3, 1 | 1990-04-03 |
Paged memory management unit which evaluates access permissions when creating translator
Grant 4,890,223 - Cruess , et al. December 26, 1 | 1989-12-26 |
Paged memory management unit capable of selectively supporting multiple address spaces
Grant 4,800,489 - Moyer , et al. January 24, 1 | 1989-01-24 |
Paged memory management unit having stack change control register
Grant 4,766,537 - Zolnowsky August 23, 1 | 1988-08-23 |
Paged memory management unit having variable number of translation table levels
Grant 4,763,250 - Keshlear , et al. August 9, 1 | 1988-08-09 |
Paged memory management unit capable of selectively supporting multiple address spaces
Grant 4,763,244 - Moyer , et al. August 9, 1 | 1988-08-09 |
Method and apparatus for selectively evaluating an effective address for a coprocessor
Grant 4,758,978 - Cruess , et al. July 19, 1 | 1988-07-19 |
Method and apparatus for validating prefetched instruction
Grant 4,757,445 - Zolnowsky , et al. * July 12, 1 | 1988-07-12 |
Method and apparatus for executing an instruction contingent upon a condition present in another data processor
Grant 4,750,110 - Mothersole , et al. June 7, 1 | 1988-06-07 |
Cache disable for a data processor
Grant 4,740,889 - Motersole , et al. April 26, 1 | 1988-04-26 |
Method and apparatus for coordinating execution of an instruction by a selected coprocessor
Grant 4,731,736 - Mothersole , et al. March 15, 1 | 1988-03-15 |
Method and apparatus for coordinating execution of an instruction by a coprocessor
Grant 4,729,094 - Zolnowsky , et al. March 1, 1 | 1988-03-01 |
Method and apparatus for limiting bus utilization
Grant 4,719,567 - Whittington , et al. January 12, 1 | 1988-01-12 |
Coprocessor instruction format
Grant 4,715,013 - MacGregor , et al. December 22, 1 | 1987-12-22 |
Method and apparatus for validating prefetched instruction
Grant 4,710,866 - Zolnowsky , et al. December 1, 1 | 1987-12-01 |
Bus master capable of relinquishing bus on request and retrying bus cycle
Grant 4,602,327 - LaViolette , et al. July 22, 1 | 1986-07-22 |
Method and apparatus for a compare and swap instruction
Grant 4,584,640 - MacGregor , et al. April 22, 1 | 1986-04-22 |
Data processor which can repeat the execution of instruction loops with minimal instruction fetches
Grant 4,566,063 - Zolnowsky , et al. January 21, 1 | 1986-01-21 |
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