loadpatents
name:-0.011855840682983
name:-0.010087013244629
name:-0.0012240409851074
Zistl; Christian Patent Filings

Zistl; Christian

Patent Applications and Registrations

Patent applications and USPTO patent grants for Zistl; Christian.The latest application filed is for "method of patterning a low-k dielectric using a hard mask".

Company Profile
0.10.7
  • Zistl; Christian - Dresden DE
  • Zistl; Christian - Austin TX
  • Zistl, Christian - Oresden DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging
Grant 8,698,312 - Werking , et al. April 15, 2
2014-04-15
Resist trim process to define small openings in dielectric layers
Grant 7,737,021 - Dakshina-Murthy , et al. June 15, 2
2010-06-15
Method of patterning a low-k dielectric using a hard mask
Grant 7,416,992 - Lehr , et al. August 26, 2
2008-08-26
Method of patterning a low-k dielectric using a hard mask
App 20060246711 - Lehr; Matthias ;   et al.
2006-11-02
Simultaneous formation of device and backside contacts on wafers having a buried insulator layer
Grant 7,005,380 - Aminpur , et al. February 28, 2
2006-02-28
Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging
App 20050242435 - Werking, James ;   et al.
2005-11-03
Depth of focus (DOF) for trench-first-via-last (TFVL) damascene processing with hard mask and low viscosity photoresist
Grant 6,881,665 - Tsui , et al. April 19, 2
2005-04-19
Semiconductor device with a copper line having an increased resistance against electromigration and a method of forming the same
Grant 6,806,191 - Zistl , et al. October 19, 2
2004-10-19
Simultaneous formation of device and backside contacts on wafers having a buried insulator layer
App 20040121599 - Aminpur, Massud ;   et al.
2004-06-24
Diffusion barrier layer in semiconductor substrates to reduce copper contamination from the back side
App 20030232466 - Zistl, Christian ;   et al.
2003-12-18
Semiconductor device with a copper line having an increased resistance against electromigration and a method of forming the same
App 20030224599 - Zistl, Christian ;   et al.
2003-12-04
Locally increasing sidewall density by ion implantation
Grant 6,610,594 - Apelgren , et al. August 26, 2
2003-08-26
Locally increasing sidewall density by ion implantation
App 20030013296 - Apelgren, Eric M. ;   et al.
2003-01-16
Resist trim process to define small openings in dielectric layers
Grant 6,500,755 - Dakshina-Murthy , et al. December 31, 2
2002-12-31
Resist trim process to define small openings in dielectric layers
App 20020068436 - Dakshina-Murthy, Srikanteswara ;   et al.
2002-06-06
Method of forming a semiconductor device with metal silicide regions
Grant 6,268,255 - Besser , et al. July 31, 2
2001-07-31

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