Zier; Michael
Patent Applications and Registrations
Patent applications and USPTO patent grants for Zier; Michael.The latest application filed is for "technique for defining active regions of semiconductor devices with reduced lithography effort".
- Zier; Michael - Dresden DE
| Patent | Date |
|---|---|
| Technique For Defining Active Regions Of Semiconductor Devices With Reduced Lithography Effort App 20190043752 - Smith; Elliot John ; et al. | 2019-02-07 |
| Technique for defining active regions of semiconductor devices with reduced lithography effort Grant 10,199,259 - Smith , et al. Fe | 2019-02-05 |
| Contacting SOI subsrates Grant 10,068,918 - Haufe , et al. September 4, 2 | 2018-09-04 |
| Standard Cell Layout And Method Of Arranging A Plurality Of Standard Cells App 20170358565 - Hensel; Ulrich ; et al. | 2017-12-14 |
| Gate Protection For Hv-stress Application App 20170336467 - Mikalo; Ricardo Pablo. ; et al. | 2017-11-23 |
| Reducing antenna effects in SOI devices Grant 9,773,811 - Lorenz , et al. September 26, 2 | 2017-09-26 |
| Reducing Antenna Effects In Soi Devices App 20170243894 - Lorenz; Ingolf ; et al. | 2017-08-24 |
| Contacting Soi Substrates App 20170104005 - Haufe; Christian ; et al. | 2017-04-13 |
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