loadpatents
name:-0.01992392539978
name:-0.04118013381958
name:-0.00069999694824219
Ziegler; Michael L. Patent Filings

Ziegler; Michael L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ziegler; Michael L..The latest application filed is for "delay queues based on delay remaining".

Company Profile
0.42.27
  • Ziegler; Michael L. - Roseville CA
  • Ziegler; Michael L - Roseville CA US
  • Ziegler; Michael L. - Campbell CA
  • Ziegler; Michael L. - Whitinsville MA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Consistency checking for credit-based control of data communications
Grant 9,426,083 - Ziegler August 23, 2
2016-08-23
Packet descriptor trace indicators
Grant 9,237,082 - Ziegler January 12, 2
2016-01-12
Delay queues based on delay remaining
Grant 9,112,820 - Ziegler August 18, 2
2015-08-18
Target issue intervals
Grant 8,908,711 - Ziegler December 9, 2
2014-12-09
Delays based on packet sizes
Grant 8,879,571 - Ziegler November 4, 2
2014-11-04
Node interface indicators
Grant 8,830,838 - Ziegler September 9, 2
2014-09-09
Corrective actions based on probabilities
Grant 8,689,049 - Ziegler , et al. April 1, 2
2014-04-01
Delay Queues Based On Delay Remaining
App 20140036695 - Ziegler; Michael L.
2014-02-06
Packet Descriptor Trace Indicators
App 20130250777 - Ziegler; Michael L.
2013-09-26
Reassembly of mini-packets in a buffer
Grant 8,537,859 - Traub , et al. September 17, 2
2013-09-17
Indicators for streams associated with messages
Grant 8,539,113 - Ziegler September 17, 2
2013-09-17
Distribution Trees With Stages
App 20130223443 - Ziegler; Michael L.
2013-08-29
Corrective Actions Based On Probabilities
App 20130117605 - Ziegler; Michael L. ;   et al.
2013-05-09
Delays Based On Packet Sizes
App 20130111050 - Ziegler; Michael L.
2013-05-02
Target Issue Intervals
App 20130107891 - Ziegler; Michael L.
2013-05-02
Node Interface Indicators
App 20130064140 - ZIEGLER; Michael L.
2013-03-14
Response Messages Based On Pending Requests
App 20130028266 - Ziegler; Michael L. ;   et al.
2013-01-31
Sending Request Messages To Nodes Indicated As Unresolved
App 20130024541 - Ziegler; Michael L. ;   et al.
2013-01-24
Indicators For Streams Associated With Messages
App 20120320910 - Ziegler; Michael L.
2012-12-20
Sending Request Messages Over Designated Communications Channels
App 20120320909 - Ziegler; Michael L. ;   et al.
2012-12-20
Processing element having dual control stores to minimize branch latency
Grant 8,046,569 - Ziegler October 25, 2
2011-10-25
Reassembly Of Mini-packets In A Buffer
App 20110211591 - Traub; Steven ;   et al.
2011-09-01
Consistency Checking For Credit-based Control Of Data Communications
App 20110075555 - Ziegler; Michael L.
2011-03-31
Method for allowing distributed high performance coherent memory with full error containment
Grant 7,478,262 - Dickey , et al. January 13, 2
2009-01-13
Processing element having dual control stores to minimize branch latency
App 20080270773 - Ziegler; Michael L.
2008-10-30
Routing communications to a storage area network
Grant 7,346,802 - Adams , et al. March 18, 2
2008-03-18
System and method for preloading cache memory in response to an occurrence of a context switch
Grant 7,191,319 - Dwyer , et al. March 13, 2
2007-03-13
Routing communications to a storage area network
App 20050188243 - Adams, Aland B. ;   et al.
2005-08-25
Program control flow conditioned on presence of requested data in cache memory
Grant 6,925,535 - Ziegler August 2, 2
2005-08-02
Method and apparatus for varying the level of correctness checks executed when performing correctness checks opportunistically using spare instruction slots
Grant 6,880,153 - Thompson , et al. April 12, 2
2005-04-12
Method and apparatus for resuming execution of a failed computer program
Grant 6,874,138 - Ziegler , et al. March 29, 2
2005-03-29
Method for allowing distributed high performance coherent memory with full error containment
App 20040153842 - Dickey, Kent A. ;   et al.
2004-08-05
Compiler-based checkpointing for support of error recovery
Grant 6,708,288 - Ziegler , et al. March 16, 2
2004-03-16
Method for allowing distributed high performance coherent memory with full error containment
Grant 6,651,193 - Dickey , et al. November 18, 2
2003-11-18
Program control flow conditioned on presence of requested data in cache memory
App 20030046494 - Ziegler, Michael L.
2003-03-06
Method and apparatus for enabling a compiler to reduce cache misses by performing pre-fetches in the event of context switch
App 20030023663 - Thompson, Carol L. ;   et al.
2003-01-30
System and method for dynamically updating memory address mappings
Grant 6,473,845 - Hornung , et al. October 29, 2
2002-10-29
Queue-based predictive flow control mechanism with indirect determination of queue fullness
Grant 6,304,932 - Ziegler , et al. October 16, 2
2001-10-16
Method and apparatus for transferring data in a computer system
Grant 6,199,144 - Arora , et al. March 6, 2
2001-03-06
Cache tag system for use with multiple processors including the most recently requested processor identification
Grant 5,737,757 - Hassoun , et al. April 7, 1
1998-04-07
Partial cache line write transactions in a computing system with a write back cache
Grant 5,586,297 - Bryg , et al. December 17, 1
1996-12-17
Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
Grant 5,530,933 - Frink , et al. June 25, 1
1996-06-25
Fast pipelined distributed arbitration scheme
Grant 5,519,838 - Ziegler , et al. May 21, 1
1996-05-21
Computer with multiple processors having varying priorities for access to a multi-element memory
Grant 5,133,059 - Ziegler , et al. July 21, 1
1992-07-21
Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
Grant 4,794,521 - Ziegler , et al. December 27, 1
1988-12-27
Digital computer with multisection cache
Grant 4,783,736 - Ziegler , et al. November 8, 1
1988-11-08
Data processing system having unique bus control protocol
Grant 4,622,630 - Vora , et al. November 11, 1
1986-11-11
Universal memory
Grant 4,513,372 - Ziegler , et al. April 23, 1
1985-04-23
Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing
Grant 4,493,033 - Ziegler , et al. January 8, 1
1985-01-08
Data processing system having a unique instruction processor system
Grant 4,398,243 - Holberger , et al. August 9, 1
1983-08-09
Data processing system
Grant 4,386,399 - Rasala , et al. May 31, 1
1983-05-31

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