| Patent | Date |
|---|
Scheduling simultaneous optimization of multiple very-large-scale-integration designs
Grant 10,789,400 - Liu , et al. September 29, 2 | 2020-09-29 |
Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time
Grant 10,263,519 - Joshi , et al. | 2019-04-16 |
Scheduling Simultaneous Optimization Of Multiple Very-large-scale-integration Designs
App 20180322226 - Liu; Hung-Yi ; et al. | 2018-11-08 |
Scheduling simultaneous optimization of multiple very-large-scale-integration designs
Grant 10,083,268 - Liu , et al. September 25, 2 | 2018-09-25 |
Enhanced parameter tuning for very-large-scale integration synthesis
Grant 10,002,221 - Liu , et al. June 19, 2 | 2018-06-19 |
Enhanced parameter tuning for very-large-scale integration synthesis
Grant 9,934,344 - Liu , et al. April 3, 2 | 2018-04-03 |
Synthesis tuning system for VLSI design optimization
Grant 9,910,949 - Gristede , et al. March 6, 2 | 2018-03-06 |
Intra-run design decision process for circuit synthesis
Grant 9,703,920 - Berry , et al. July 11, 2 | 2017-07-11 |
Intra-run design decision process for circuit synthesis
Grant 9,690,900 - Berry , et al. June 27, 2 | 2017-06-27 |
Enhanced Parameter Tuning For Very-large-scale Integration Synthesis
App 20170177752 - Liu; Hung-Yi ; et al. | 2017-06-22 |
Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time
Grant 9,660,530 - Joshi , et al. May 23, 2 | 2017-05-23 |
Enhanced Parameter Tuning For Very-large-scale Integration Synthesis
App 20170109456 - Liu; Hung-Yi ; et al. | 2017-04-20 |
Enhanced parameter tuning for very-large-scale integration synthesis
Grant 9,619,602 - Liu , et al. April 11, 2 | 2017-04-11 |
Scheduling Simultaneous Optimization Of Multiple Very-large-scale-integration Designs
App 20170083639 - Liu; Hung-Yi ; et al. | 2017-03-23 |
Scheduling Simultaneous Optimization Of Multiple Very-large-scale-integration Designs
App 20170083659 - Liu; Hung-Yi ; et al. | 2017-03-23 |
Scheduling simultaneous optimization of multiple very-large-scale-integration designs
Grant 9,600,623 - Liu , et al. March 21, 2 | 2017-03-21 |
Synthesis Tuning System for VLSI Design Optimization
App 20170076018 - Gristede; George D. ; et al. | 2017-03-16 |
Enhanced parameter tuning for very-large-scale integration synthesis
Grant 9,582,627 - Liu , et al. February 28, 2 | 2017-02-28 |
Resonant Virtual Supply Booster For Synchronous Digital Circuits Having A Predictable Evaluate Time
App 20170025949 - Joshi; Rajiv V. ; et al. | 2017-01-26 |
Resonant Virtual Supply Booster For Synchronous Digital Circuits Having A Predictable Evaluate Time
App 20170025948 - Joshi; Rajiv V. ; et al. | 2017-01-26 |
Intra-run Design Decision Process For Circuit Synthesis
App 20170004243 - Berry; Christopher J. ; et al. | 2017-01-05 |
Intra-run Design Decision Process For Circuit Synthesis
App 20170004246 - Berry; Christopher J. ; et al. | 2017-01-05 |
Synthesis tuning system for VLSI design optimization
Grant 9,529,951 - Gristede , et al. December 27, 2 | 2016-12-27 |
Enhanced Parameter Tuning For Very-large-scale Integration Synthesis
App 20160147916 - Liu; Hung-Yi ; et al. | 2016-05-26 |
Enhanced Parameter Tuning For Very-large-scale Integration Synthesis
App 20160147932 - Liu; Hung-Yi ; et al. | 2016-05-26 |
Synthesis Tuning System for VLSI Design Optimization
App 20150347641 - Gristede; George D. ; et al. | 2015-12-03 |
Graphical method and product to assign physical attributes to entities in a high level descriptive language used for VLSI chip design
Grant 8,954,914 - Badar , et al. February 10, 2 | 2015-02-10 |
Specifying circuit level connectivity during circuit design synthesis
Grant 8,839,162 - Amundson , et al. September 16, 2 | 2014-09-16 |
Structured Latch and Local-Clock-Buffer Planning
App 20130326451 - Cho; Minsik ; et al. | 2013-12-05 |
Network flow based datapath bit slicing
Grant 8,566,761 - Xiang , et al. October 22, 2 | 2013-10-22 |
Soft hierarchy-based physical synthesis for large-scale, high-performance circuits
Grant 8,516,412 - Cho , et al. August 20, 2 | 2013-08-20 |
Structured latch and local-clock-buffer planning
Grant 8,495,552 - Cho , et al. July 23, 2 | 2013-07-23 |
Network Flow Based Datapath Bit Slicing
App 20130132915 - Cho; Minsik ; et al. | 2013-05-23 |
Soft Hierarchy-based Physical Synthesis For Large-scale, High-performance Circuits
App 20130055176 - Cho; Minsik ; et al. | 2013-02-28 |
Converged large block and structured synthesis for high performance microprocessor designs
Grant 8,271,920 - Cho , et al. September 18, 2 | 2012-09-18 |
Converged Large Block And Structured Synthesis For High Performance Microprocessor Designs
App 20120054699 - Cho; Minsik ; et al. | 2012-03-01 |
Specifying Circuit Level Connectivity During Circuit Design Synthesis
App 20120017186 - Amundson; Michael D. ; et al. | 2012-01-19 |
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