Ziaja; Thomas A.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Ziaja; Thomas A..The latest application filed is for "method and circuit for scan dump of latch array".
- Ziaja; Thomas A. - Austin TX
- Ziaja; Thomas A - Austin TX
| Patent | Date |
|---|---|
| Method and circuit for row scannable latch array Grant 11,443,822 - Ziaja , et al. September 13, 2 | 2022-09-13 |
| Method and circuit for scan dump of latch array Grant 11,443,823 - Ziaja , et al. September 13, 2 | 2022-09-13 |
| Method And Circuit For Row Scannable Latch Array App 20220139477 - ZIAJA; Thomas A. ; et al. | 2022-05-05 |
| Method And Circuit For Scan Dump Of Latch Array App 20220139478 - ZIAJA; Thomas A. ; et al. | 2022-05-05 |
| At-speed test of memory arrays using scan Grant 9,401,223 - Ziaja , et al. July 26, 2 | 2016-07-26 |
| At-Speed Test of Memory Arrays Using Scan App 20150325314 - Ziaja; Thomas A ; et al. | 2015-11-12 |
| Method and apparatus for testing delay faults Grant 8,074,133 - Ziaja , et al. December 6, 2 | 2011-12-06 |
| At-speed scan testing of memory arrays Grant 8,065,572 - Ziaja , et al. November 22, 2 | 2011-11-22 |
| At-speed Scan Testing Of Memory Arrays App 20100332924 - Ziaja; Thomas A. ; et al. | 2010-12-30 |
| Method And Apparatus For Testing Delay Faults App 20100037111 - Ziaja; Thomas A. ; et al. | 2010-02-11 |
| Automatic generation and validation of memory test models Grant 6,813,201 - Zarrineh , et al. November 2, 2 | 2004-11-02 |
| Automatic generation and validation of memory test models App 20030076723 - Zarrineh, Kamran ; et al. | 2003-04-24 |
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