ZHU; John Jianhong

Patent Applications and Registrations

Patent applications and USPTO patent grants for ZHU; John Jianhong.The latest application filed is for "subtractive damascene formation of hybrid interconnections".

Company Profile

9.34.50

ZHU; John Jianhong - San Diego CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Subtractive Damascene Formation Of Hybrid Interconnections App 20220262723 - BAO; Junjing ; et al.	2022-08-18
Hybrid low resistance metal lines Grant 11,404,373 - Bao , et al. August 2, 2	2022-08-02
Hybrid conductor integration in power rail Grant 11,302,638 - Zhu , et al. April 12, 2	2022-04-12
Metal Interconnect Wrap Around With Graphene App 20220068703 - BAO; Junjing ; et al.	2022-03-03
Metal-oxide-metal capacitor from subtractive back-end-of-line scheme Grant 11,239,307 - Zhu , et al. February 1, 2	2022-02-01
Metal-oxide-metal Capacitor From Subtractive Back-end-of-line Scheme App 20210343830 - ZHU; John Jianhong ; et al.	2021-11-04
Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections Grant 11,152,347 - Song , et al. October 19, 2	2021-10-19
Transistor Circuit With Asymmetrical Drain And Source App 20210320175 - YANG; Haining ; et al.	2021-10-14
Hybrid Back-end-of-line (beol) Dielectric For High Capacitance Density Metal-oxide-metal (mom) Capacitor App 20210320059 - LU; Ye ; et al.	2021-10-14
Hybrid Conductor Integration In Power Rail App 20210217699 - ZHU; John Jianhong ; et al.	2021-07-15
Shunt power rail with short line effect Grant 11,038,344 - Zhu , et al. June 15, 2	2021-06-15
Hybrid Low Resistance Metal Lines App 20210167006 - BAO; Junjing ; et al.	2021-06-03
Spacer-based Conductor Cut App 20210143056 - ZHU; John Jianhong ; et al.	2021-05-13
Super Via Integration In Integrated Circuits App 20210125862 - ZHU; John Jianhong ; et al.	2021-04-29
Nanosheet Transistor Stack App 20210005604 - GE; Lixin ; et al.	2021-01-07
MIDDLE-OF-LINE (MOL) COMPLEMENTARY POWER RAIL(S) IN INTEGRATED CIRCUITS (ICs) FOR REDUCED SEMICONDUCTOR DEVICE RESISTANCE App 20200105670 - Zhu; John Jianhong ; et al.	2020-04-02
Shunt Power Rail With Short Line Effect App 20200044440 - ZHU; John Jianhong ; et al.	2020-02-06
Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells Grant 10,497,702 - Zhu , et al. De	2019-12-03
Integrated circuits (ICs) employing additional output vertical interconnect access(es) (VIA(s)) coupled to a circuit output VIA to decrease circuit output resistance Grant 10,483,200 - Yang , et al. Nov	2019-11-19
Cell Circuits Formed In Circuit Cells Employing Offset Gate Cut Areas In A Non-active Area For Routing Transistor Gate Cross-con App 20190319022 - Song; Stanley Seungchul ; et al.	2019-10-17
Systems And Methods For Dummy Gate Tie-offs In A Self-aligned Gate Contact (sagc) Cell App 20190296126 - Song; Stanley Seungchul ; et al.	2019-09-26
Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs) Grant 10,354,912 - Xu , et al. July 16, 2	2019-07-16
Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop Grant 10,283,526 - Zhu , et al.	2019-05-07
Semiconductor device having an airgap defined at least partially by a protective structure Grant 10,163,792 - Zhu , et al. Dec	2018-12-25
Metal-oxide Semiconductor (mos) Standard Cells Employing Electrically Coupled Source Regions And Supply Rails To Relax Source-drain Tip-to-tip Spacing Between Adjacent Mos Standard Cells App 20180301447 - Zhu; John Jianhong ; et al.	2018-10-18
Semiconductor device having a gap defined therein Grant 10,079,293 - Xu , et al. September 18, 2	2018-09-18
Vertically stacked nanowire field effect transistors Grant 10,043,796 - Machkaoutsan , et al. August 7, 2	2018-08-07
Semiconductor Devices Employing Reduced Area Conformal Contacts To Reduce Parasitic Capacitance, And Related Methods App 20180212029 - Xu; Jeffrey Junhao ; et al.	2018-07-26
Standard Cell Circuits Employing Voltage Rails Electrically Coupled To Metal Shunts For Reducing Or Avoiding Increases In Voltage Drop App 20180175060 - Zhu; John Jianhong ; et al.	2018-06-21
Variable interconnect pitch for improved performance Grant 9,984,029 - Rim , et al. May 29, 2	2018-05-29
Semiconductor Device Having A Gap Defined Therein App 20180114848 - Xu; Jeffrey Junhao ; et al.	2018-04-26
Contact wrap around structure Grant 9,953,979 - Xu , et al. April 24, 2	2018-04-24
Systems and methods to reduce parasitic capacitance Grant 9,941,156 - Gu , et al. April 10, 2	2018-04-10
Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device Grant 9,941,154 - Song , et al. April 10, 2	2018-04-10
Semiconductor device having a gap defined therein Grant 9,871,121 - Xu , et al. January 16, 2	2018-01-16
Integrated circuit device featuring an antifuse and method of making same Grant 9,842,802 - Wang , et al. December 12, 2	2017-12-12
Self-aligned structure Grant 9,799,560 - Song , et al. October 24, 2	2017-10-24
Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices Grant 9,793,164 - Machkaoutsan , et al. October 17, 2	2017-10-17
FORMING SELF-ALIGNED VERTICAL INTERCONNECT ACCESSES (VIAs) IN INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS (ICs) App 20170271202 - Xu; Jeffrey Junhao ; et al.	2017-09-21
Vertically Stacked Nanowire Field Effect Transistors App 20170221884 - Machkaoutsan; Vladimir ; et al.	2017-08-03
Integrated circuit devices and methods Grant 9,721,891 - Xu , et al. August 1, 2	2017-08-01
Self-aligned Metal Cut And Via For Back-end-of-line (beol) Processes For Semiconductor Integrated Circuit (ic) Fabrication, And Related Processes And Devices App 20170140986 - Machkaoutsan; Vladimir ; et al.	2017-05-18
Middle-of-line integration methods and semiconductor devices Grant 9,653,399 - Zhu , et al. May 16, 2	2017-05-16
High density area efficient thin-oxide decoupling capacitor using conductive gate resistor Grant 9,633,996 - Ge , et al. April 25, 2	2017-04-25
Reverse Self Aligned Double Patterning Process For Back End Of Line Fabrication Of A Semiconductor Device App 20170110364 - Song; Stanley Seungchul ; et al.	2017-04-20
Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods Grant 9,620,454 - Zhu , et al. April 11, 2	2017-04-11
Integrated Circuit Devices And Methods App 20170092587 - Xu; Jeffrey Junhao ; et al.	2017-03-30
Multi-cell Transistor Device And Method Of Making Same With Cut Polyoxide Process For Self-aligned Contacts App 20170077090 - SONG; Stanley Seungchul ; et al.	2017-03-16
Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device Grant 9,564,361 - Song , et al. February 7, 2	2017-02-07
Integrated circuit devices and methods Grant 9,543,248 - Xu , et al. January 10, 2	2017-01-10
Structure For Coupling Metal Layer Interconnects In A Semiconductor Device App 20160343661 - GUPTA; Mukul ; et al.	2016-11-24
Integrated circuit device featuring an antifuse and method of making same Grant 9,502,424 - Wang , et al. November 22, 2	2016-11-22
Capacitor from second level middle-of-line layer in combination with decoupling capacitors Grant 9,478,490 - Zhu , et al. October 25, 2	2016-10-25
Systems and methods of forming a reduced capacitance device Grant 9,472,453 - Xu , et al. October 18, 2	2016-10-18
Systems And Methods To Reduce Parasitic Capacitance App 20160293475 - Gu; Shiqun ; et al.	2016-10-06
Self-aligned Structure App 20160293485 - Song; Stanley Seungchul ; et al.	2016-10-06
Middle-of-line Integration Methods And Semiconductor Devices App 20160240485 - Zhu; John Jianhong ; et al.	2016-08-18
Selective Conductive Barrier Layer Formation App 20160233126 - XU; Jeffrey Junhao ; et al.	2016-08-11
Integrated Circuit Devices And Methods App 20160211216 - Xu; Jeffrey Junhao ; et al.	2016-07-21
Grounding dummy gate in scaled layout design Grant 9,379,058 - Song , et al. June 28, 2	2016-06-28
High Resistance Metal Etch-stop Plate For Metal Flyover Layer App 20160172456 - Li; Xia ; et al.	2016-06-16
Contact Wrap Around Structure App 20160148936 - XU; Jeffrey Junhao ; et al.	2016-05-26
Barrier Structure App 20160141250 - Bao; Junjing ; et al.	2016-05-19
Selective conductive barrier layer formation Grant 9,343,357 - Xu , et al. May 17, 2	2016-05-17
Methods Of Forming A Metal-insulator-semiconductor (mis) Structure And A Dual Contact Device App 20160126144 - Xu; Jeffrey Junhao ; et al.	2016-05-05
MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS (ICs) EMPLOYING LOCAL INTERCONNECTS OF METAL LINES USING AN ELONGATED VIA, AND RELATED METHODS App 20160079175 - Zhu; John Jianhong ; et al.	2016-03-17
Tie-off Structures For Middle-of-line (mol) Manufactured Integrated Circuits, And Related Methods App 20160079167 - Zhu; John Jianhong ; et al.	2016-03-17
Capacitor From Second Level Middle-of-line Layer In Combination With Decoupling Capacitors App 20160071795 - ZHU; John Jianhong ; et al.	2016-03-10
Device Including Cavity And Self-aligned Contact And Method Of Fabricating The Same App 20160049487 - Xu; Jeffrey Junhao ; et al.	2016-02-18
Semiconductor Device Having An Airgap Defined At Least Partially By A Protective Structure App 20160027726 - Zhu; John Jianhong ; et al.	2016-01-28
Semiconductor device having high mobility channel Grant 9,245,971 - Yang , et al. January 26, 2	2016-01-26
Via material selection and processing Grant 9,196,583 - Zhu , et al. November 24, 2	2015-11-24
Via Material Selection And Processing App 20150325515 - ZHU; John Jianhong ; et al.	2015-11-12
Back End Of Line (beol) Local Optimization To Improve Product Performance App 20150303145 - ZHU; John Jianhong ; et al.	2015-10-22
Variable Interconnect Pitch For Improved Performance App 20150301973 - RIM; Kern ; et al.	2015-10-22
Methods Of Forming A Metal-insulator-semiconductor (mis) Structure And A Dual Contact Device App 20150270134 - Xu; Jeffrey Junhao ; et al.	2015-09-24
Systems And Methods Of Forming A Reduced Capacitance Device App 20150262875 - Xu; Jeffrey Junhao ; et al.	2015-09-17
Semiconductor Device Having A Gap Defined Therein App 20150255571 - Xu; Jeffrey Junhao ; et al.	2015-09-10
Selective Conductive Barrier Layer Formation App 20150249038 - XU; Jeffrey Junhao ; et al.	2015-09-03
Grounding Dummy Gate In Scaled Layout Design App 20150235948 - SONG; Stanley Seungchul ; et al.	2015-08-20
Local interconnect structures for high density Grant 9,024,418 - Zhu , et al. May 5, 2	2015-05-05
Semiconductor Device Having High Mobility Channel App 20150091060 - Yang; Bin ; et al.	2015-04-02
Reverse Self Aligned Double Patterning Process For Back End Of Line Fabrication Of A Semiconductor Device App 20150076704 - Song; Stanley Seungchul ; et al.	2015-03-19
Integrated Circuit Device Featuring An Antifuse And Method Of Making Same App 20140210043 - Wang; Zhongze ; et al.	2014-07-31

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