| Patent | Date |
|---|
Device Package Substrate Structure And Method Therefor
App 20220059441 - Foong; Chee Seng ; et al. | 2022-02-24 |
3D chip testing through micro-C4 interface
Grant 11,193,953 - Garibay , et al. December 7, 2 | 2021-12-07 |
Electronic module power supply
Grant 10,765,002 - Christo , et al. Sep | 2020-09-01 |
Substrate dielectric crack prevention using interleaved metal plane
Grant 10,537,019 - Zhou , et al. Ja | 2020-01-14 |
Electronic Module Power Supply
App 20190306977 - Christo; Michael A. ; et al. | 2019-10-03 |
3d Chip Testing Through Micro-c4 Interface
App 20190265273 - Garibay; Victor A. ; et al. | 2019-08-29 |
3D chip testing through micro-C4 interface
Grant 10,371,717 - Garibay , et al. | 2019-08-06 |
Electronic module power supply
Grant 10,362,674 - Christo , et al. | 2019-07-23 |
Electronic Module Power Supply
App 20190014662 - Christo; Michael A. ; et al. | 2019-01-10 |
Package materials monitor and method therefor
Grant 10,147,654 - Cejka , et al. De | 2018-12-04 |
Electronic module power supply
Grant 10,080,285 - Christo , et al. September 18, 2 | 2018-09-18 |
Multiple interconnections between die
Grant 10,037,970 - Clegg , et al. July 31, 2 | 2018-07-31 |
Interconnect array pattern with a 3:1 signal-to-ground ratio
Grant 9,972,566 - Chen , et al. May 15, 2 | 2018-05-15 |
Package to board interconnect structure with built-in reference plane structure
Grant 9,974,174 - Wenzel , et al. May 15, 2 | 2018-05-15 |
Package Materials Monitor And Method Therefor
App 20180112972 - CEJKA; STANLEY ANDREW ; et al. | 2018-04-26 |
Package To Board Interconnect Structure With Built-in Reference Plane Structure
App 20180116050 - WENZEL; Robert ; et al. | 2018-04-26 |
Multiple Interconnections Between Die
App 20180068980 - Clegg; David ; et al. | 2018-03-08 |
3d Chip Testing Through Micro-c4 Interface
App 20170336440 - Garibay; Victor A. ; et al. | 2017-11-23 |
3D chip testing through micro-C4 interface
Grant 9,726,691 - Garibay , et al. August 8, 2 | 2017-08-08 |
Interconnect array pattern with a 3:1 signal-to-ground ratio
Grant 9,646,925 - Chen , et al. May 9, 2 | 2017-05-09 |
Distribution of power vias in a multi-layer circuit board
Grant 9,600,619 - Chen , et al. March 21, 2 | 2017-03-21 |
Distribution of power vias in a multi-layer circuit board
Grant 9,594,865 - Chen , et al. March 14, 2 | 2017-03-14 |
OPTIMIZING POWER DISTRIBUTION FROM A POWER SOURCE THROUGH A C4 SOLDER BALL GRID INTERCONNECTED THROUGH SILICON VIAS IN INTERMEDIATE INTEGRATED CIRCUIT CHIP CONNECTED TO CIRCUITRY IN AN UPPER INTERGRATED CIRCUIT CHIP THROUGH A GRID OF MICRO uC4 SOLDER BALLS
App 20170053899 - Bartley; Gerald K. ; et al. | 2017-02-23 |
Interconnect Array Pattern With A 3:1 Signal-to-ground Ratio
App 20170048967 - Chen; Zhaoqing ; et al. | 2017-02-16 |
Interconnect array pattern with a 3:1 signal-to-ground ratio
Grant 9,543,241 - Chen , et al. January 10, 2 | 2017-01-10 |
Pad-to-pad Embedded Capacitance In Lieu Of Signal Via Transitions In Printed Circuit Boards
App 20170006709 - Chen; Zhaoqing ; et al. | 2017-01-05 |
Pad-to-pad Embedded Capacitance In Lieu Of Signal Via Transitions In Printed Circuit Boards
App 20170004923 - Chen; Zhaoqing ; et al. | 2017-01-05 |
Distribution Of Power Vias In A Multi-layer Circuit Board
App 20160342724 - Chen; Zhaoqing ; et al. | 2016-11-24 |
Distribution Of Power Vias In A Multi-layer Circuit Board
App 20160342723 - Chen; Zhaoqing ; et al. | 2016-11-24 |
Electronic module power supply
Grant 9,456,498 - Christo , et al. September 27, 2 | 2016-09-27 |
Electronic Module Power Supply
App 20160255722 - Christo; Michael A. ; et al. | 2016-09-01 |
Interconnect Array Pattern With A 3:1 Signal-to-ground Ratio
App 20160149611 - Chen; Zhaoqing ; et al. | 2016-05-26 |
Interconnect Array Pattern With A 3:1 Signal-to-ground Ratio
App 20160150638 - Chen; Zhaoqing ; et al. | 2016-05-26 |
OPTIMIZING POWER DISTRIBUTION FROM A POWER SOURCE THROUGH A C4 SOLDER BALL GRID INTERCONNECTED THROUGH SILICON VIAS IN INTERMEDIATE INTEGRATED CIRCUIT CHIP CONNECTED TO CIRCUITRY IN AN UPPER INTEGRATED CIRCUIT CHIP THROUGH A GRID OF MICRO uC4 SOLDER BALLS
App 20160071822 - Bartley; Gerald K. ; et al. | 2016-03-10 |
Reducing power grid noise in a processor while minimizing performance loss
Grant 9,146,772 - Eisen , et al. September 29, 2 | 2015-09-29 |
Reducing power grid noise in a processor while minimizing performance loss
Grant 9,141,421 - Eisen , et al. September 22, 2 | 2015-09-22 |
3d Chip Testing Through Micro-c4 Interface
App 20150192633 - Garibay; Victor A. ; et al. | 2015-07-09 |
Reducing Power Grid Noise In A Processor While Minimizing Performance Loss
App 20140157033 - Eisen; Lee E. ; et al. | 2014-06-05 |
Reducing Power Grid Noise In A Processor While Minimizing Performance Loss
App 20140157277 - Eisen; Lee E. ; et al. | 2014-06-05 |
Method for making high-speed ceramic modules with hybrid referencing scheme for improved performance and reduced cost
Grant 8,683,413 - Becker , et al. March 25, 2 | 2014-03-25 |
Electronic Module Power Supply
App 20140029221 - Christo; Michael A. ; et al. | 2014-01-30 |
Method of attaching an electronic module power supply
Grant 8,572,840 - Christo , et al. November 5, 2 | 2013-11-05 |
Method For Making High-speed Ceramic Modules With Hybrid Referencing Scheme For Improved Performance And Reduced Cost
App 20130252379 - Becker; Wiren D ; et al. | 2013-09-26 |
Reducing crosstalk in the design of module nets
Grant 8,407,644 - Cabrera , et al. March 26, 2 | 2013-03-26 |
High-speed ceramic modules with hybrid referencing scheme for improved performance and reduced cost
Grant 8,339,803 - Becker , et al. December 25, 2 | 2012-12-25 |
Network flow based module bottom surface metal pin assignment
Grant 8,261,226 - Becker , et al. September 4, 2 | 2012-09-04 |
Electronic Module Power Supply
App 20120081859 - Christo; Michael A. ; et al. | 2012-04-05 |
High-Speed Ceramic Modules with Hybrid Referencing Scheme for Improved Performance and Reduced Cost
App 20110132650 - Becker; Wiren D. ; et al. | 2011-06-09 |
Reducing Crosstalk In The Design Of Module Nets
App 20110031627 - Cabrera; Dulce M. Altabella ; et al. | 2011-02-10 |
Silicon interposer testing for three dimensional chip stack
Grant 7,863,106 - Christo , et al. January 4, 2 | 2011-01-04 |
System and method for power domain optimization
Grant 7,844,925 - Zhou , et al. November 30, 2 | 2010-11-30 |
Silicon Interposer Testing For Three Dimensional Chip Stack
App 20100155888 - Christo; Michael Anthony ; et al. | 2010-06-24 |
Auto-Router Performing Simultaneous Placement of Signal and Return Paths
App 20090193383 - Christo; Michael A. ; et al. | 2009-07-30 |
Flow based package pin assignment
Grant 7,533,360 - Ren , et al. May 12, 2 | 2009-05-12 |
System and Method for Power Domain Optimization
App 20080295041 - Zhou; Tingdong ; et al. | 2008-11-27 |
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