Zheng; Jia Zhen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Zheng; Jia Zhen.The latest application filed is for "semiconductor local interconnect and contact".

Company Profile

0.71.54

Zheng; Jia Zhen - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor local interconnect and contact Grant 8,304,834 - Yelehanka , et al. November 6, 2	2012-11-06
Non-volatile memory manufacturing method using STI trench implantation Grant 8,236,646 - Chan , et al. August 7, 2	2012-08-07
Integrated circuit with protected implantation profiles and method for the formation thereof Grant 7,501,683 - Lai , et al. March 10, 2	2009-03-10
MOSFET device with low gate contact resistance Grant 7,382,027 - Verma , et al. June 3, 2	2008-06-03
Thyristor-based SRAM Grant 7,285,804 - Quek , et al. October 23, 2	2007-10-23
Process to reduce substrate effects by forming channels under inductor devices and around analog blocks Grant 7,250,669 - Chan , et al. July 31, 2	2007-07-31
Self-aligned lateral heterojunction bipolar transistor Grant 7,238,971 - Li , et al. July 3, 2	2007-07-03
Horizontal tram Grant 7,183,590 - Zheng , et al. February 27, 2	2007-02-27
Ultra-thin gate oxide through post decoupled plasma nitridation anneal Grant 7,176,094 - Zhong , et al. February 13, 2	2007-02-13
Semiconductor Local Interconnect And Contact App 20060281253 - Yelehanka; Pradeep Ramachandramurthy ; et al.	2006-12-14
Thyristor-based SRAM Grant 7,148,522 - Quek , et al. December 12, 2	2006-12-12
Charge pump current source Grant 7,132,878 - Chen , et al. November 7, 2	2006-11-07
Semiconductor local interconnect and contact Grant 7,119,005 - Yelehanka , et al. October 10, 2	2006-10-10
Integrated Circuit With Protected Implantation Profiles And Method For The Formation Thereof App 20060220110 - Lai; Tommy ; et al.	2006-10-05
Horizontal Tram App 20060214185 - Zheng; Jia Zhen ; et al.	2006-09-28
Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits App 20060207965 - Ramaghandramurthy Pradeep; Yelehanka ; et al.	2006-09-21
High K artificial lattices for capacitor applications to use in Cu or Al BEOL Grant 7,095,073 - Balakumar , et al. August 22, 2	2006-08-22
Horizontal TRAM and method for the fabrication thereof Grant 7,081,378 - Zheng , et al. July 25, 2	2006-07-25
Integrated circuit with protected implantation profiles and method for the formation thereof Grant 7,067,362 - Lai , et al. June 27, 2	2006-06-27
Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy Grant 7,049,201 - Verma , et al. May 23, 2	2006-05-23
Charge pump current source App 20060103450 - Chen; Tupei ; et al.	2006-05-18
Multi-level gate SONOS flash memory device with high voltage oxide and method for the fabrication thereof Grant 7,015,101 - Zheng , et al. March 21, 2	2006-03-21
Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth Grant 6,972,237 - Verma , et al. December 6, 2	2005-12-06
Self-aligned lateral heterojunction bipolar transistor App 20050196931 - Li, Jian Xun ; et al.	2005-09-08
Thyristor-based SRAM App 20050167664 - Quek, Elgin ; et al.	2005-08-04
Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact Grant 6,924,202 - Li , et al. August 2, 2	2005-08-02
Horizontal TRAM and method for the fabrication thereof App 20050148118 - Zheng, Jia Zhen ; et al.	2005-07-07
Heterojunction BiCMOS integrated circuits and method therefor App 20050145953 - Chan, Lap ; et al.	2005-07-07
Method of making direct contact on gate by using dielectric stop layer App 20050136573 - Rajverma, Purakh ; et al.	2005-06-23
Self-aligned lateral heterojunction bipolar transistor Grant 6,908,824 - Li , et al. June 21, 2	2005-06-21
Method to fill a trench and tunnel by using ALD seed layer and electroless plating Grant 6,903,013 - Chan , et al. June 7, 2	2005-06-07
Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth App 20050116254 - Verma, Purakh Raj ; et al.	2005-06-02
High K artificial lattices for capacitor applications to use in Cu or Al BEOL App 20050118780 - Balakumar, Subramanian ; et al.	2005-06-02
Method using quasi-planar double gated fin field effect transistor process for the fabrication of a thyristor-based static read/write random-access memory Grant 6,897,111 - Quek , et al. May 24, 2	2005-05-24
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing App 20050101083 - Ang, Chew Hoe ; et al.	2005-05-12
Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy App 20050101038 - Verma, Purakh Raj ; et al.	2005-05-12
Heterojunction Bicmos Semiconductor App 20050098834 - Zheng, Jia Zhen ; et al.	2005-05-12
Thyristor-based SRAM App 20050098794 - Quek, Elgin ; et al.	2005-05-12
Self-aligned Lateral Heterojunction Bipolar Transistor App 20050101096 - Li, Jian Xun ; et al.	2005-05-12
Non-volatile memory and manufacturing method using STI trench implantation App 20050101102 - Chan, Tze Ho Simon ; et al.	2005-05-12
Method of fabricating circular or angular spiral MIM capacitors App 20050086780 - Shao, Kai ; et al.	2005-04-28
Method to pattern small features by using a re-flowable hard mask App 20050089777 - Ang, Chew-Hoe ; et al.	2005-04-28
Integrated circuit with protected implantation profiles and method for the formation thereof App 20050085056 - Lai, Tommy ; et al.	2005-04-21
Heterojunction BiCMOS semiconductor Grant 6,881,976 - Zheng , et al. April 19, 2	2005-04-19
Heterojunction bipolar transistor using reverse emitter window App 20050079678 - Verma, Purakh Raj ; et al.	2005-04-14
Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact App 20050079658 - Li, Jian Xun ; et al.	2005-04-14
Process to reduce substrate effects by forming channels under inductor devices and around analog blocks Grant 6,869,884 - Chan , et al. March 22, 2	2005-03-22
Method Of Making Direct Contact On Gate By Using Dielectric Stop Layer App 20050059216 - Verma, Purakh Raj ; et al.	2005-03-17
Method of making direct contact on gate by using dielectric stop layer Grant 6,861,317 - Verma , et al. March 1, 2	2005-03-01
Thyristor-based Sram And Method For The Fabrication Thereof App 20050026337 - Quek, Elgin ; et al.	2005-02-03
Thyistor-based SRAM and method using quasi-planar finfet process for the fabrication thereof App 20050026343 - Quek, Elgin ; et al.	2005-02-03
Thyristor-based SRAM and method for the fabrication thereof Grant 6,849,481 - Quek , et al. February 1, 2	2005-02-01
Process to reduce substrate effects by forming channels under inductor devices and around analog blocks App 20050009357 - Chan, Lap ; et al.	2005-01-13
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing Grant 6,841,441 - Ang , et al. January 11, 2	2005-01-11
Formation of small gates beyond lithographic limits App 20040266155 - Ang, Chew Hoe ; et al.	2004-12-30
High K artificial lattices for capacitor applications to use in CU or AL BEOL Grant 6,830,971 - Balakumar , et al. December 14, 2	2004-12-14
Method to pattern small features by using a re-flowable hard mask Grant 6,828,082 - Ang , et al. December 7, 2	2004-12-07
Method of blocking nitrogen from thick gate oxide during dual gate CMP Grant 6,821,904 - Pradeep , et al. November 23, 2	2004-11-23
Method to fill a trench and tunnel by using ALD seed layer and electroless plating App 20040229457 - Chan, Lap ; et al.	2004-11-18
Method to fabricate elevated source/drain transistor with large area for silicidation Grant 6,780,691 - Cha , et al. August 24, 2	2004-08-24
Method of manufacturing semiconductor local interconnect and contact App 20040155269 - Yelehanka, Pradeep Ramachandramurthy ; et al.	2004-08-12
Method of forming a high performance and low cost CMOS device Grant 6,762,085 - Zheng , et al. July 13, 2	2004-07-13
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing App 20040132271 - Ang, Chew Hoe ; et al.	2004-07-08
Method to form a self-aligned CMOS inverter using vertical device integration Grant 6,747,314 - Sundaresan , et al. June 8, 2	2004-06-08
Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth Grant 6,743,291 - Ang , et al. June 1, 2	2004-06-01
Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape Grant 6,734,082 - Zheng , et al. May 11, 2	2004-05-11
High K artificial lattices for capacitor applications to use in CU or AL BEOL App 20040087101 - Balakumar, Subramanian ; et al.	2004-05-06
Method of forming a surface coating layer within an opening within a body by atomic layer deposition Grant 6,716,693 - Chan , et al. April 6, 2	2004-04-06
Method of forming a high performance and low cost CMOS device App 20040063264 - Zheng, Jia Zhen ; et al.	2004-04-01
Method for forming variable-K gate dielectric Grant 6,709,934 - Lee , et al. March 23, 2	2004-03-23
Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization Grant 6,709,912 - Ang , et al. March 23, 2	2004-03-23
Process to reduce substrate effects by forming channels under inductor devices and around analog blocks App 20040038542 - Chan, Lap ; et al.	2004-02-26
Method to fabricate elevated source/drain transistor with large area for silicidation App 20040033668 - Cha, Randall Cher Liang ; et al.	2004-02-19
Method for forming gate insulating layer having multiple dielectric constants and multiple equivalent oxide thicknesses App 20040029321 - Ang, Chew Hoe ; et al.	2004-02-12
Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape App 20040029353 - Zheng, Jia Zhen ; et al.	2004-02-12
Method of blocking nitrogen from thick gate oxide during dual gate CMP App 20040023506 - Pradeep, Yelehanka Ramachandramurthy ; et al.	2004-02-05
Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth App 20040007170 - Ang, Chew Hoe ; et al.	2004-01-15
Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits App 20040004054 - Pradeep, Yelehanka Ramachandramurthy ; et al.	2004-01-08
HDP SRO liner for beyond 0.18 um STI gap-fill App 20040005781 - Huang, Liu ; et al.	2004-01-08
Triple gate oxide process with high-k gate dielectric Grant 6,670,248 - Ang , et al. December 30, 2	2003-12-30
Method to fabricate a single gate with dual work-functions Grant 6,664,153 - Ang , et al. December 16, 2	2003-12-16
Method for forming L-shaped spacers with precise width control Grant 6,664,156 - Ang , et al. December 16, 2	2003-12-16
Method of fabricating variable length vertical transistors Grant 6,632,712 - Ang , et al. October 14, 2	2003-10-14
Ultra-thin gate oxide through post decoupled plasma nitridation anneal App 20030170956 - Zhong, Dong ; et al.	2003-09-11
Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask Grant 6,610,604 - Ang , et al. August 26, 2	2003-08-26
Forming dual gate oxide thickness on vertical transistors by ion implantation Grant 6,610,575 - Ang , et al. August 26, 2	2003-08-26
Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components Grant 6,608,362 - Kai , et al. August 19, 2	2003-08-19
Method to pattern small features by using a re-flowable hard mask App 20030152871 - Ang, Chew-Hoe ; et al.	2003-08-14
Method to fabricate a single gate with dual work-functions App 20030153139 - Ang, Chew Hoe ; et al.	2003-08-14
Method of fabricating CMOS device with dual gate electrode Grant 6,605,501 - Ang , et al. August 12, 2	2003-08-12
Method Of Forming Small Transistor Gates By Using Self-aligned Reverse Spacer As A Hard Mask App 20030148617 - Ang, Chew-Hoe ; et al.	2003-08-07
Method to form elevated source/drain using poly spacer Grant 6,566,208 - Pan , et al. May 20, 2	2003-05-20
Method to form a self-aligned CMOS inverter using vertical device integration App 20030075758 - Sundaresan, Ravi ; et al.	2003-04-24
Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel Grant 6,544,824 - Pradeep , et al. April 8, 2	2003-04-08
Method to form elevated source/drain using poly spacer App 20030022450 - Pan, Yang ; et al.	2003-01-30
Method to improve latchup by forming selective sloped staircase STI structure to use in the I/0 or latchup sensitive area App 20030017710 - Yang, Pan ; et al.	2003-01-23
Method for forming variable-K gate dielectric App 20020173106 - Lee, James Yong Meng ; et al.	2002-11-21
Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner Grant 6,468,877 - Pradeep , et al. October 22, 2	2002-10-22
Method to form a self-aligned CMOS inverter using vertical device integration Grant 6,461,900 - Sundaresan , et al. October 8, 2	2002-10-08
Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation Grant 6,436,770 - Leung , et al. August 20, 2	2002-08-20
Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate Grant 6,429,109 - Zheng , et al. August 6, 2	2002-08-06
Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers App 20020102784 - Lee, James Yong Meng ; et al.	2002-08-01
Method For Fabricating A Self Aligned S/d Cmos Device On Insulated Layer By Forming A Trench Along The Sti And Fill With Oxide App 20020102798 - Zheng, Jia Zhen ; et al.	2002-08-01
Method for forming variable-K gate dielectric App 20020100947 - Lee, James Yong Meng ; et al.	2002-08-01
Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) App 20020098655 - Zheng, Jia Zhen ; et al.	2002-07-25
Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge Grant 6,417,056 - Quek , et al. July 9, 2	2002-07-09
Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide Grant 6,417,054 - Zheng , et al. July 9, 2	2002-07-09
Method to form a low parasitic capacitance pseudo-SOI CMOS device Grant 6,403,485 - Quek , et al. June 11, 2	2002-06-11
Method to form a recessed source drain on a trench side wall with a replacement gate technique Grant 6,380,088 - Chan , et al. April 30, 2	2002-04-30
Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon Grant 6,313,008 - Leung , et al. November 6, 2	2001-11-06
Method to form smaller channel with CMOS device by isotropic etching of the gate materials Grant 6,306,715 - Chan , et al. October 23, 2	2001-10-23
Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials Grant 6,300,177 - Sundaresan , et al. October 9, 2	2001-10-09
Gap filling process in integrated circuits using low dielectric constant materials App 20010012687 - Xu, Yi ; et al.	2001-08-09
Method of forming MOS/CMOS devices with dual or triple gate oxide Grant 6,268,251 - Zhong , et al. July 31, 2	2001-07-31
Method to form gate oxides of different thicknesses on a silicon substrate Grant 6,235,591 - Balasubramanian , et al. May 22, 2	2001-05-22
Gap filling process in integrated circuits using low dielectric constant materials Grant 6,207,554 - Xu , et al. March 27, 2	2001-03-27
Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer Grant 6,140,237 - Chan , et al. October 31, 2	2000-10-31
Plasma enhanced chemical vapor deposited (PECVD) silicon nitride barrier layer for high density plasma chemical vapor deposited (HDP-CVD) dielectric layer Grant 6,127,238 - Liao , et al. October 3, 2	2000-10-03
Method of making a copper interconnect with top barrier layer Grant 6,100,196 - Chan , et al. August 8, 2	2000-08-08
Method for planarizing a low dielectric constant spin-on polymer using nitride etch stop Grant 6,069,069 - Chooi , et al. May 30, 2	2000-05-30
Method of planarization of an intermetal dielectric layer using chemical mechanical polishing Grant 5,948,700 - Zheng , et al. September 7, 1	1999-09-07
Method for reducing microloading in an etchback of spin-on-glass or polymer Grant 5,930,677 - Zheng , et al. July 27, 1	1999-07-27
Barrier layer Grant 5,900,672 - Chan , et al. May 4, 1	1999-05-04
Method of manufacturing copper interconnect with top barrier layer Grant 5,744,376 - Chan , et al. April 28, 1	1998-04-28
Method for shallow trench isolation Grant 5,728,621 - Zheng , et al. March 17, 1	1998-03-17