Zhao; Jie-Hua

Patent Applications and Registrations

Patent applications and USPTO patent grants for Zhao; Jie-Hua.The latest application filed is for "systems and methods for implementing a scalable system".

Company Profile

4.14.20

Zhao; Jie-Hua - Cupertino CA
Zhao; Jie-Hua - Austin TX
ZHAO; Jie-Hua - Plant TX
Zhao; Jie-Hua - Plano TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Systems And Methods For Implementing A Scalable System App 20220231687 - Dabral; Sanjay ; et al.	2022-07-21
Systems and methods for implementing a scalable system Grant 11,309,895 - Dabral , et al. April 19, 2	2022-04-19
Multiple Chip Module Trenched Lid and Low Coefficient of Thermal Expansion Stiffener Ring App 20210305227 - Chen; Wei ; et al.	2021-09-30
Systems And Methods For Implementing A Scalable System App 20200389172 - Dabral; Sanjay ; et al.	2020-12-10
Systems and methods for implementing a scalable system Grant 10,742,217 - Dabral , et al. A	2020-08-11
Systems And Methods For Implementing A Scalable System App 20190319626 - Dabral; Sanjay ; et al.	2019-10-17
Method of lower profile MEMS package with stress isolations Grant 9,656,856 - Jiang , et al. May 23, 2	2017-05-23
Methodology to achieve zero warpage for IC package Grant 9,633,953 - Hsu , et al. April 25, 2	2017-04-25
Method Of Lower Profile Mems Package With Stress Isolations App 20160340175 - Jiang; Tongbi ; et al.	2016-11-24
Method of lower profile MEMS package with stress isolations Grant 9,446,941 - Jiang , et al. September 20, 2	2016-09-20
Method Of Lower Profile Mems Package With Stress Isolations App 20160167949 - Jiang; Tongbi ; et al.	2016-06-16
Methodology To Achieve Zero Warpage For Ic Package App 20160071807 - Hsu; Jun Chung ; et al.	2016-03-10
PoP structure with electrically insulating material between packages Grant 9,263,426 - Zhao , et al. February 16, 2	2016-02-16
PoP STRUCTURE WITH ELECTRICALLY INSULATING MATERIAL BETWEEN PACKAGES App 20150118795 - Zhao; Jie-Hua ; et al.	2015-04-30
PoP structure with electrically insulating material between packages Grant 8,963,311 - Zhao , et al. February 24, 2	2015-02-24
PoP STRUCTURE WITH ELECTRICALLY INSULATING MATERIAL BETWEEN PACKAGES App 20140084487 - Zhao; Jie-Hua ; et al.	2014-03-27
Circuit device with at least partial packaging and method for forming Grant 8,072,062 - Leal , et al. December 6, 2	2011-12-06
Electromigration-Resistant Flip-Chip Solder Joints App 20100219528 - ZHAO; Jie-Hua ; et al.	2010-09-02
Mechanical integrity evaluation of low-k devices with bump shear Grant 7,622,309 - Su , et al. November 24, 2	2009-11-24
Method of forming crack arrest features in embedded device build-up package and package thereof Grant 7,553,753 - Zhao , et al. June 30, 2	2009-06-30
Electromigration-Resistant Flip-Chip Solder Joints App 20080251927 - Zhao; Jie-Hua ; et al.	2008-10-16
Circuit Device With At Least Partial Packaging And Method For Forming App 20080142960 - Leal; George R. ; et al.	2008-06-19
Stress-improved Flip-chip Semiconductor Device Having Half-etched Leadframe App 20080135990 - Coyle; Anthony L. ; et al.	2008-06-12
Leadframe finger design to ensure lead-locking for enhanced fatigue life of bonding wire in an overmolded package App 20080122049 - Zhao; Jie-Hua ; et al.	2008-05-29
Circuit device with at least partial packaging and method for forming Grant 7,361,987 - Leal , et al. April 22, 2	2008-04-22
Method Of Forming Crack Arrest Features In Embedded Device Build-up Package And Package Thereof App 20080057696 - Zhao; Jie-Hua ; et al.	2008-03-06
Integrated circuit having structural support for a flip-chip interconnect pad and method therefor Grant 7,247,552 - Pozder , et al. July 24, 2	2007-07-24
Mechanical integrity evaluation of low-k devices with bump shear App 20060292711 - Su; Peng ; et al.	2006-12-28
Integrated circuit having structural support for a flip-chip interconnect pad and method therefor App 20060154470 - Pozder; Scott K. ; et al.	2006-07-13
Circuit device with at least partial packaging and method for forming App 20060012036 - Leal; George R. ; et al.	2006-01-19
Circuit device with at least partial packaging, exposed active surface and a voltage reference plane Grant 6,921,975 - Leal , et al. July 26, 2	2005-07-26
Circuit device with at least partial packaging and method for forming Grant 6,838,776 - Leal , et al. January 4, 2	2005-01-04
Circuit device with at least partial packaging and method for forming App 20040207077 - Leal, George R. ; et al.	2004-10-21
Circuit device with at least partial packaging and method for forming App 20040207068 - Leal, George R. ; et al.	2004-10-21

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