Zhang; Chihong

Patent Applications and Registrations

Patent applications and USPTO patent grants for Zhang; Chihong.The latest application filed is for "graphics instruction operands alias".

Company Profile

2.20.14

Zhang; Chihong - San Diego CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Deferred GPR allocation for texture/load instruction block Grant 11,204,765 - Du , et al. December 21, 2	2021-12-21
Graphics instruction operands alias Grant 11,132,760 - Du , et al. September 28, 2	2021-09-28
General purpose register and wave slot allocation in graphics processing Grant 11,094,103 - Du , et al. August 17, 2	2021-08-17
Graphics Instruction Operands Alias App 20210183005 - Du; Yun ; et al.	2021-06-17
General Purpose Register And Wave Slot Allocation In Graphics Processing App 20200312006 - DU; Yun ; et al.	2020-10-01
General purpose register allocation in streaming processor Grant 10,558,460 - Du , et al. Feb	2020-02-11
General Purpose Register Allocation In Streaming Processor App 20180165092 - Du; Yun ; et al.	2018-06-14
Per-instance preamble for graphics processing Grant 9,799,094 - Chen , et al. October 24, 2	2017-10-24
Utilizing pipeline registers as intermediate storage Grant 9,747,104 - Chen , et al. August 29, 2	2017-08-29
Skipping of data storage Grant 9,665,370 - Du , et al. May 30, 2	2017-05-30
Inter-processor communication techniques in a multiple-processor computing platform Grant 9,645,866 - Bourd , et al. May 9, 2	2017-05-09
Inter-processor communication techniques in a multiple-processor computing platform Grant 9,626,234 - Bourd , et al. April 18, 2	2017-04-18
Skipping Of Data Storage App 20160054998 - Du; Yun ; et al.	2016-02-25
Optimizing texture commands for graphics processing unit Grant 9,256,408 - Zhang , et al. February 9, 2	2016-02-09
Utilizing Pipeline Registers As Intermediate Storage App 20150324196 - Chen; Lin ; et al.	2015-11-12
Inter-processor Communication Techniques In A Multiple-processor Computing Platform App 20150097849 - Bourd; Alexei Vladimirovich ; et al.	2015-04-09
Inter-processor communication techniques in a multiple-processor computing platform Grant 8,937,622 - Bourd , et al. January 20, 2	2015-01-20
Loop transformation for computer compiler optimization Grant 8,732,679 - Udayakumaran , et al. May 20, 2	2014-05-20
Optimizing Texture Commands For Graphics Processing Unit App 20130191816 - Zhang; Weifeng ; et al.	2013-07-25
Shader compile system and method Grant 8,495,602 - Chen , et al. July 23, 2	2013-07-23
System and method of mapping shader variables into physical registers Grant 8,379,032 - Chen , et al. February 19, 2	2013-02-19
Efficient Conditional Flow Control Compilation App 20120284701 - Tsai; Ming-Chang ; et al.	2012-11-08
Inter-processor Communication Techniques In A Multiple-processor Computing Platform App 20120069029 - Bourd; Alexei V. ; et al.	2012-03-22
Inter-processor Communication Techniques In A Multiple-processor Computing Platform App 20120069035 - Bourd; Alexei V. ; et al.	2012-03-22
Loop Transformation for Computer Compiler Optimization App 20110231830 - Udayakumaran; Sumesh ; et al.	2011-09-22
System And Method Of Mapping Shader Variables Into Physical Registers App 20090085919 - Chen; Lin ; et al.	2009-04-02
Shader Compile System And Method App 20090089763 - Chen; Lin ; et al.	2009-04-02

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