Zechmann; Arno

Patent Applications and Registrations

Patent applications and USPTO patent grants for Zechmann; Arno.The latest application filed is for "wafer based beol process for chip embedding".

Company Profile

4.6.7

Zechmann; Arno - Villach AT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor wafer dicing crack prevention using chip peripheral trenches Grant 10,903,120 - Zechmann , et al. January 26, 2	2021-01-26
Wafer Based Beol Process For Chip Embedding App 20190259874 - Ganitzer; Paul ; et al.	2019-08-22
Semiconductor wafer dicing crack prevention using chip peripheral trenches Grant 10,256,149 - Zechmann , et al.	2019-04-09
Semiconductor Wafer Dicing Crack Prevention Using Chip Peripheral Trenches App 20190043757 - Zechmann; Arno ; et al.	2019-02-07
Semiconductor Wafer Dicing Crack Prevention Using Chip Peripheral Trenches App 20180247869 - Zechmann; Arno ; et al.	2018-08-30
Semiconductor Wafer And Method App 20170170282 - Zechmann; Arno ; et al.	2017-06-15
Semiconductor wafer and method Grant 9,660,037 - Zechmann , et al. May 23, 2	2017-05-23
Semiconductor Device Having Gold Metallization Structures App 20160336272 - Zechmann; Arno	2016-11-17
Method of electrodepositing gold on a copper seed layer to form a gold metallization structure Grant 9,425,090 - Zechmann August 23, 2	2016-08-23
Method Of Electrodepositing Gold On A Copper Seed Layer To Form A Gold Metallization Structure App 20160086847 - Zechmann; Arno	2016-03-24
Wafer Based Beol Process For Chip Embedding App 20150221764 - Ganitzer; Paul ; et al.	2015-08-06
Integrated circuit including power transistor cells and a connecting line Grant 8,502,274 - Matoy , et al. August 6, 2	2013-08-06

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