Zaveri; Ketan H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Zaveri; Ketan H..The latest application filed is for "apparatus and methods for adjusting performance of programmable logic devices".

Company Profile

0.10.5

Zaveri; Ketan H. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Techniques for providing clock signals in an integrated circuit Grant 9,024,673 - Venkata , et al. May 5, 2	2015-05-05
Apparatus and methods for adjusting performance of programmable logic devices Grant 8,198,914 - Lee , et al. June 12, 2	2012-06-12
Apparatus and methods for adjusting performance of programmable logic devices App 20110204919 - Lee; Andy L. ; et al.	2011-08-25
Apparatus and methods for adjusting performance of programmable logic devices Grant 7,936,184 - Lee , et al. May 3, 2	2011-05-03
Method and system for reducing static leakage current in programmable logic devices Grant 7,295,036 - Zaveri , et al. November 13, 2	2007-11-13
Apparatus and methods for adjusting performance of programmable logic devices App 20070200596 - Lee; Andy L. ; et al.	2007-08-30
Programmable logic device with hierarchical interconnection resources Grant 6,798,242 - Reddy , et al. September 28, 2	2004-09-28
Programmable logic device with hierarchical interconnection resources App 20030201794 - Reddy, Srinivas T. ; et al.	2003-10-30
Programmable logic device with hierarchical interconnection resources App 20030076130 - Reddy, Srinivas T. ; et al.	2003-04-24
Configurable memory structures in a programmable logic device Grant 6,462,577 - Lee , et al. October 8, 2	2002-10-08
Programmable logic device with hierarchical interconnection resources App 20020041191 - Reddy, Srinivas T. ; et al.	2002-04-11
Multifunction memory array in a programmable logic device Grant 6,356,110 - Reddy , et al. March 12, 2	2002-03-12
Programmable logic device circuitry for improving multiplier speed and/or efficiency Grant 6,323,677 - Lane , et al. November 27, 2	2001-11-27
Programmable logic device circuitry for improving multiplier speed and/or efficiency Grant 6,069,487 - Lane , et al. May 30, 2	2000-05-30
Programmable logic device with hierarchical interconnection resources Grant 5,977,793 - Reddy , et al. November 2, 1	1999-11-02

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