loadpatents
Patent applications and USPTO patent grants for Zang; Yuan.The latest application filed is for "substrate interconnections for packaged semiconductor device".
Patent | Date |
---|---|
Lead frame with dummy leads for burr mitigation during encapsulation Grant 10,037,935 - Pang , et al. July 31, 2 | 2018-07-31 |
Substrate interconnections for packaged semiconductor device Grant 9,997,445 - Yow , et al. June 12, 2 | 2018-06-12 |
Substrate Interconnections For Packaged Semiconductor Device App 20180114748 - Yow; Kai Yun ;   et al. | 2018-04-26 |
Lead Frame Based Semiconductor Die Package App 20140361421 - Bai; Zhigang ;   et al. | 2014-12-11 |
Lead frame based semiconductor die package Grant 8,901,721 - Bai , et al. December 2, 2 | 2014-12-02 |
Semiconductor Device And Method Of Assembling Same App 20130249071 - Yao; Jinzhong ;   et al. | 2013-09-26 |
Lead Frame For Semiconductor Package App 20080283980 - Gao; Wei ;   et al. | 2008-11-20 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.