loadpatents
name:-0.0027492046356201
name:-0.011048078536987
name:-0.0010550022125244
Zandveld; Frederik Patent Filings

Zandveld; Frederik

Patent Applications and Registrations

Patent applications and USPTO patent grants for Zandveld; Frederik.The latest application filed is for "processor architecture with independently addressable memory banks for storing instructions to be executed".

Company Profile
0.9.1
  • Zandveld; Frederik - 5621 BA Eindhoven NL
  • Zandveld, Frederik - Eindhoven NL
  • Zandveld; Frederik - CL Bergeyk NL
  • Zandveld; Frederik - Hulsberg NL
  • Zandveld; Frederik - Beekbergen NL
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Processor architecture with independently addressable memory banks for storing instructions to be executed
Grant 7,124,282 - Zandveld , et al. October 17, 2
2006-10-17
Processor architecture with independently addressable memory banks for storing instructions to be executed
App 20020038415 - Zandveld, Frederik ;   et al.
2002-03-28
Processor architecture with independently addressable memory banks for storing instructions to be executed
Grant 6,360,311 - Zandveld , et al. March 19, 2
2002-03-19
Solid state data processor with versatile multisource interrupt organization
Grant 6,098,144 - De Oliveira , et al. August 1, 2
2000-08-01
Method for operation of a bus system for highly flexible and quick data transmission between units connected to the bus system and configuration for carrying out the method
Grant 5,828,852 - Niedermeier , et al. October 27, 1
1998-10-27
Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface
Grant 5,659,797 - Zandveld , et al. August 19, 1
1997-08-19
Microcontroller provided with hardware for supporting debugging as based on boundary scan standard-type extensions
Grant 5,590,354 - Klapproth , et al. December 31, 1
1996-12-31
Computer system comprising a data, address and control signal bus which comprises a left bus and a right bus
Grant 4,695,944 - Zandveld , et al. September 22, 1
1987-09-22
Data processing system having a control device for controlling an intermediate memory during a bulk data transport between a source device and a destination device
Grant 4,562,534 - Zandveld , et al. December 31, 1
1985-12-31
Elimination of transient errors in a data processing system by clock control
Grant 3,868,647 - Zandveld February 25, 1
1975-02-25

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