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name:-0.01075005531311
name:-0.001007080078125
Zalesinski; Jerzy Maria Patent Filings

Zalesinski; Jerzy Maria

Patent Applications and Registrations

Patent applications and USPTO patent grants for Zalesinski; Jerzy Maria.The latest application filed is for "coaxial wiring within soi semiconductor, pcb to system for high speed operation and signal quality".

Company Profile
0.9.2
  • Zalesinski; Jerzy Maria - Essex Junction VT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality
Grant 6,943,452 - Bertin , et al. September 13, 2
2005-09-13
Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality
App 20020101723 - Bertin, Claude Louis ;   et al.
2002-08-01
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
Grant 6,410,431 - Bertin , et al. June 25, 2
2002-06-25
Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality
Grant 6,388,198 - Bertin , et al. May 14, 2
2002-05-14
High density integrated circuit packaging with chip stacking and via interconnections
Grant 6,236,115 - Gaynes , et al. May 22, 2
2001-05-22
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
App 20010001292 - Bertin, Claude Louis ;   et al.
2001-05-17
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
Grant 6,222,276 - Bertin , et al. April 24, 2
2001-04-24
High density integrated circuit packaging with chip stacking and via interconnections
Grant 6,187,678 - Gaynes , et al. February 13, 2
2001-02-13
Integrated heat exchanger for memory module
Grant 6,025,992 - Dodge , et al. February 15, 2
2000-02-15
High density integrated circuit packaging with chip stacking and via interconnections
Grant 6,002,177 - Gaynes , et al. December 14, 1
1999-12-14
Electrolytic method of depositing gold connectors on a printed circuit board
Grant 5,733,466 - Benebo , et al. March 31, 1
1998-03-31

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