| Patent | Date |
|---|
Reduced pitch laser redundancy fuse bank structure
Grant 6,597,054 - Prall , et al. July 22, 2 | 2003-07-22 |
One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture
Grant RE36,952 - Zagar , et al. November 14, 2 | 2000-11-14 |
High speed global row redundancy system
Grant 6,104,645 - Ong , et al. August 15, 2 | 2000-08-15 |
Efficient method for obtaining usable parts from a partially good memory integrated circuit
Grant 6,097,647 - Zagar , et al. August 1, 2 | 2000-08-01 |
Dynamic random-access memory having a hierarchical data path
Grant 5,999,480 - Ong , et al. December 7, 1 | 1999-12-07 |
Dynamic random access memory having decoding circuitry for partial memory blocks
Grant 5,901,105 - Ong , et al. May 4, 1 | 1999-05-04 |
Burst EDO memory address counter
Grant 5,850,368 - Ong , et al. December 15, 1 | 1998-12-15 |
Circuit for cancelling and replacing redundant elements
Grant 5,838,620 - Zagar , et al. November 17, 1 | 1998-11-17 |
Circuit and method for varying a period of an internal control signal during a test mode
Grant 5,831,918 - Merritt , et al. November 3, 1 | 1998-11-03 |
Synchronous burst extended data out dram
Grant 5,812,488 - Zagar , et al. September 22, 1 | 1998-09-22 |
Burst EDO memory device
Grant 5,802,010 - Zagar , et al. September 1, 1 | 1998-09-01 |
Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts
Grant RE35,825 - Zagar June 16, 1 | 1998-06-16 |
Efficient method for obtaining usable parts from a partially good memory integrated circuit
Grant 5,761,145 - Zagar , et al. June 2, 1 | 1998-06-02 |
Reduced pitch laser redundancy fuse bank structure
Grant 5,747,869 - Prall , et al. May 5, 1 | 1998-05-05 |
Burst EDO memory device
Grant 5,696,732 - Zagar , et al. December 9, 1 | 1997-12-09 |
Circuit for cancelling and replacing redundant elements
Grant 5,677,884 - Zagar , et al. October 14, 1 | 1997-10-14 |
Burst EDO memory device address counter
Grant 5,675,549 - Ong , et al. October 7, 1 | 1997-10-07 |
Synchronous burst extended data out DRAM
Grant 5,668,773 - Zagar , et al. September 16, 1 | 1997-09-16 |
Synchronous NAND DRAM architecture
Grant 5,666,323 - Zagar September 9, 1 | 1997-09-09 |
Burst EDO memory device
Grant 5,661,695 - Zagar , et al. August 26, 1 | 1997-08-26 |
Integrated circuit power supply having piecewise linearity
Grant 5,552,739 - Keeth , et al. September 3, 1 | 1996-09-03 |
Optimization circuitry and control for a synchronous memory device with programmable latency period
Grant 5,544,124 - Zagar , et al. August 6, 1 | 1996-08-06 |
High speed global row redundancy system
Grant 5,528,539 - Ong , et al. June 18, 1 | 1996-06-18 |
Burst EDO memory device
Grant 5,526,320 - Zagar , et al. June 11, 1 | 1996-06-11 |
Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits
Grant 5,488,583 - Ong , et al. January 30, 1 | 1996-01-30 |
One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture
Grant 5,315,177 - Zagar , et al. May 24, 1 | 1994-05-24 |
Wordline driver circuit having a directly gated pull-down device
Grant 5,311,481 - Casper , et al. May 10, 1 | 1994-05-10 |
Integrated circuit memory with asymmetric row access topology
Grant 5,311,478 - Zagar , et al. May 10, 1 | 1994-05-10 |
Wordline driver circuit having an automatic precharge circuit
Grant 5,293,342 - Casper , et al. March 8, 1 | 1994-03-08 |
CMOS logic cell for high-speed, zero-power programmable array logic devices
Grant 5,270,587 - Zagar December 14, 1 | 1993-12-14 |
Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts
Grant 5,235,550 - Zagar August 10, 1 | 1993-08-10 |
Field programmable logic array with speed optimized architecture
Grant 5,235,221 - Douglas , et al. August 10, 1 | 1993-08-10 |
Field programmable logic array with two or planes
Grant 5,220,215 - Douglas , et al. June 15, 1 | 1993-06-15 |
Nonvolatile, zero-power memory cell constructed with capacitor-like antifuses operable at less than power supply voltage
Grant 5,148,391 - Zagar September 15, 1 | 1992-09-15 |
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