Yung, Robert

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yung, Robert.The latest application filed is for "computer system and method for fetching a next instruction".

Company Profile

0.20.3

Yung, Robert - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Computer system and method for fetching a next instruction App 20020124162 - Yung, Robert ; et al.	2002-09-05
Visual instruction set for CPU with integrated graphics functions App 20020091910 - Yung, Robert	2002-07-11
Microprocessor with parallel inverse square root logic for performing graphics function on packed data elements Grant 6,385,713 - Yung	2002-05-07
Central processing unit with integrated graphics functions Grant 6,279,099 - Van Hook , et al. August 21, 2	2001-08-21
Visual instruction set for CPU with integrated graphics functions App 20010002484 - Yung, Robert	2001-05-31
Instruction result labeling in a counterflow pipeline processor Grant 6,205,538 - Yung March 20, 2	2001-03-20
Temporary pipeline register file for a superpipelined superscalar processor Grant 6,128,721 - Yung , et al. October 3, 2	2000-10-03
Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions Grant 5,996,066 - Yung November 30, 1	1999-11-30
Processor having a plurality of pipelines and a mechanism for maintaining coherency among register values in the pipelines Grant 5,956,747 - Wilhelm , et al. September 21, 1	1999-09-21
Central processing unit with integrated graphics functions Grant 5,938,756 - Van Hook , et al. August 17, 1	1999-08-17
Graphic system for masking multiple non-contiguous bytes having decode logic to selectively activate each of the control lines based on the mask register bits Grant 5,931,945 - Yung , et al. August 3, 1	1999-08-03
Central processing unit with integrated graphics functions Grant 5,933,157 - Van Hook , et al. August 3, 1	1999-08-03
Microprocessor having a cache memory system using multi-level cache set prediction Grant 5,918,245 - Yung June 29, 1	1999-06-29
Computer processor having a register file with reduced read and/or write port bandwidth Grant 5,761,475 - Yung , et al. June 2, 1	1998-06-02
Interleaving block operations employing an instruction set capable of delaying block-store instructions related to outstanding block-load instructions in a computer system Grant 5,761,472 - Howell , et al. June 2, 1	1998-06-02
Method and apparatus for using double precision addressable registers for single precision data Grant 5,752,271 - Yung May 12, 1	1998-05-12
Central processing unit with integrated graphics functions Grant 5,734,874 - Van Hook , et al. March 31, 1	1998-03-31
Rapid register file access by limiting access to a selectable register subset Grant 5,721,868 - Yung , et al. February 24, 1	1998-02-24
Method and apparatus for performing pipeline store instructions using a single cache access pipestage Grant 5,717,896 - Yung , et al. February 10, 1	1998-02-10
Scoreboard table for a counterflow pipeline processor with instruction packages and result packages Grant 5,682,493 - Yung , et al. October 28, 1	1997-10-28
Apparatus and method for distributed control in a processor architecture Grant 5,592,679 - Yung January 7, 1	1997-01-07
Method and apparatus for rapidly retrieving data from a physically addressed data storage structure using address page crossing predictive annotations Grant 5,548,739 - Yung August 20, 1	1996-08-20
Apparatus for dynamic register management in a floating point unit Grant 5,546,554 - Yung , et al. August 13, 1	1996-08-13

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