Yuan; Leo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yuan; Leo.The latest application filed is for "automated calibration of i/o over a multi-variable eye window".

Company Profile

0.10.7

Yuan; Leo - Los Altos CA
Yuan; Leo - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Automated calibration of I/O over a multi-variable eye window Grant 7,296,104 - Smith , et al. November 13, 2	2007-11-13
Noise margin self-diagnostic receiver logic Grant 7,130,340 - Jong , et al. October 31, 2	2006-10-31
Automated calibration of I/O over a multi-variable eye window App 20060009931 - Smith; Brian L. ; et al.	2006-01-12
Automated calibration of I/O over a multi-variable eye window Grant 6,944,692 - Smith , et al. September 13, 2	2005-09-13
Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection Grant 6,937,680 - Fong , et al. August 30, 2	2005-08-30
System and method for testing operational transmissions of an integrated circuit Grant 6,880,118 - Chen , et al. April 12, 2	2005-04-12
Method and apparatus for detecting valid clock signals at a clock receiver circuit Grant 6,737,892 - Jong , et al. May 18, 2	2004-05-18
I/O test methodology App 20030080769 - Chen, Cecilia T. ; et al.	2003-05-01
Automated calibration of I/O over a multi-variable eye window App 20030051086 - Smith, Brian L. ; et al.	2003-03-13
Apparatus For On-chip Reference Voltage Generator For Receivers In High Speed Single-ended Data Link App 20030034829 - Wu, Chung-Hsiao R. ; et al.	2003-02-20
Method and circuitry for a pre-emphasis scheme for single-ended center taped terminated high speed digital signaling Grant 6,518,792 - Jong , et al. February 11, 2	2003-02-11
Method And Circuitry For A Pre-emphasis Scheme For Single-ended Center Taped Terminated High Speed Digital Signaling App 20020186056 - Jong, Jyh-Ming ; et al.	2002-12-12
Digital data transmission via multi-valued logic signals generated using multiple drive states each causing a different amount of current to flow through a termination resistor Grant 6,477,205 - Doblar , et al. November 5, 2	2002-11-05
Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection App 20020154718 - Fong, Wai ; et al.	2002-10-24
Method and apparatus for detecting valid clock signals at a clock receiver circuit App 20020078392 - Jong, Jyh-Ming ; et al.	2002-06-20
Method and apparatus for dynamic termination logic of data buses Grant 6,239,619 - Yuan , et al. May 29, 2	2001-05-29
Transmission line terminator-decoupling capacitor chip for off-chip driver Grant 4,553,050 - Feinberg , et al. November 12, 1	1985-11-12

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