Yuan; Jinyong

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yuan; Jinyong.The latest application filed is for "structures for lut-based arithmetic in plds".

Company Profile

0.38.5

Yuan; Jinyong - Cupertino CA
Yuan; Jinyong - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Structures For Lut-based Arithmetic In Plds App 20170322775 - Padalia; Ketan ; et al.	2017-11-09
Structures for LUT-based arithmetic in PLDs Grant 9,658,830 - Padalia , et al. May 23, 2	2017-05-23
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 9,172,378 - Hutton , et al. October 27, 2	2015-10-27
Register retiming technique Grant 9,053,274 - van Antwerpen , et al. June 9, 2	2015-06-09
Register retiming technique Grant 8,806,399 - van Antwerpen , et al. August 12, 2	2014-08-12
Structures for LUT-based arithmetic in PLDs Grant 8,788,550 - Padalia , et al. July 22, 2	2014-07-22
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 8,601,424 - Hutton , et al. December 3, 2	2013-12-03
Reassembling scattered logic blocks in integrated circuits Grant 8,443,327 - Bin Mohd Razha , et al. May 14, 2	2013-05-14
Graphical user aid for technology migration and associated methods Grant 8,397,185 - Perry , et al. March 12, 2	2013-03-12
Flexible RAM clock enable Grant 8,271,821 - Yuan , et al. September 18, 2	2012-09-18
Reassembling Scattered Logic Blocks In Integrated Circuits App 20120216165 - Razha; Mohd Mowardi Bin Mohd ; et al.	2012-08-23
Partial compilation of circuit design with new software version to obtain a complete compiled design Grant 8,245,163 - Yuan , et al. August 14, 2	2012-08-14
Graphical user aid for technology migration and associated methods Grant 8,191,020 - Perry , et al. May 29, 2	2012-05-29
Gated clock conversion Grant 8,006,206 - Yuan August 23, 2	2011-08-23
Methods of verifying functional equivalence between FPGA and structured ASIC logic cells Grant 7,992,110 - Yuan , et al. August 2, 2	2011-08-02
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 7,890,910 - Hutton , et al. February 15, 2	2011-02-15
SAT-based technology mapping framework Grant 7,725,871 - Safarpour , et al. May 25, 2	2010-05-25
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Grant 7,705,628 - Hutton , et al. April 27, 2	2010-04-27
Graphical user aid for technology migration and associated methods Grant 7,631,284 - Perry , et al. December 8, 2	2009-12-08
User-directed timing-driven synthesis Grant 7,587,688 - Van Antwerpen , et al. September 8, 2	2009-09-08
Structures for LUT-based arithmetic in PLDs Grant 7,558,812 - Padalia , et al. July 7, 2	2009-07-07
Flexible RAM Clock Enable App 20080253220 - Yuan; Jinyong ; et al.	2008-10-16
Gated clock conversion Grant 7,424,689 - Yuan September 9, 2	2008-09-09
Method and apparatus for reducing synthesis runtime Grant 7,415,693 - van Antwerpen , et al. August 19, 2	2008-08-19
Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations Grant 7,406,668 - Pedersen , et al. July 29, 2	2008-07-29
Flexible RAM clock enable Grant 7,397,726 - Yuan , et al. July 8, 2	2008-07-08
SAT-based technology mapping framework Grant 7,386,828 - Safarpour , et al. June 10, 2	2008-06-10
Methods of verifying functional equivalence between FPGA and structured ASIC logic cells Grant 7,386,819 - Yuan , et al. June 10, 2	2008-06-10
Methods for improved structured ASIC design Grant 7,373,630 - Yuan May 13, 2	2008-05-13
Methods of producing application-specific integrated circuit equivalents of programmable logic Grant 7,373,631 - Yuan , et al. May 13, 2	2008-05-13
Methods for storing and naming static library cells for lookup by logic synthesis and the like Grant 7,363,596 - Park , et al. April 22, 2	2008-04-22
Methods for producing equivalent logic designs for FPGAs and structured ASIC devices Grant 7,360,197 - Schleicher, II , et al. April 15, 2	2008-04-15
Area efficient fractureable logic elements Grant 7,330,052 - Kaptanoglu , et al. February 12, 2	2008-02-12
Method and apparatus for performing mapping onto field programmable gate arrays utilizing fracturable logic cells Grant 7,308,671 - Yuan , et al. December 11, 2	2007-12-11
Technology mapping techniques for incomplete lookup tables Grant 7,249,329 - Baeckler , et al. July 24, 2	2007-07-24
Methods for creating and expanding libraries of structured ASIC logic and other functions Grant 7,246,339 - Yuan , et al. July 17, 2	2007-07-17
Area efficient fractureable logic elements App 20070063732 - Kaptanoglu; Sinan ; et al.	2007-03-22
Apparatus for emulating asynchronous clear in memory structure and method for implementing the same Grant 7,126,858 - Yuan , et al. October 24, 2	2006-10-24
Methods for creating and expanding libraries of structured ASIC logic and other functions App 20060230376 - Yuan; Jinyong ; et al.	2006-10-12

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