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Yu; Ta-Ching Patent Filings

Yu; Ta-Ching

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yu; Ta-Ching.The latest application filed is for "method of fabricating semiconductor device with reduced trench distortions".

Company Profile
7.10.9
  • Yu; Ta-Ching - Hsinchu County TW
  • YU; Ta-Ching - Zhubei City TW
  • Yu; Ta-Ching - Zhubei TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method of fabricating semiconductor device with reduced trench distortions
Grant 11,387,113 - Yen , et al. July 12, 2
2022-07-12
Method Of Fabricating Semiconductor Device With Reduced Trench Distortions
App 20210057231 - Yen; Yung-Sung ;   et al.
2021-02-25
Methods Of Defect Inspection
App 20210018848 - YU; Ta-Ching ;   et al.
2021-01-21
Method of fabricating semiconductor device with reduced trench distortions
Grant 10,818,509 - Yen , et al. October 27, 2
2020-10-27
Methods of defect inspection
Grant 10,795,270 - Yu , et al. October 6, 2
2020-10-06
Method for patterning interconnects
Grant 10,276,377 - Yen , et al.
2019-04-30
Method of Fabricating Semiconductor Device with Reduced Trench Distortions
App 20190122895 - Yen; Yung-Sung ;   et al.
2019-04-25
Methods Of Defect Inspection
App 20190064675 - YU; Ta-Ching ;   et al.
2019-02-28
Method of fabricating semiconductor device with reduced trench distortions
Grant 10,163,654 - Yen , et al. Dec
2018-12-25
Directional patterning methods
Grant 10,049,918 - Hung , et al. August 14, 2
2018-08-14
Directional Patterning Methods
App 20180090370 - Hung; Chi-Cheng ;   et al.
2018-03-29
Method Of Forming Interconnect Structures By Self-aligned Approach
App 20170338151 - Chen; Chih-Hao ;   et al.
2017-11-23
Method for Patterning Interconnects
App 20170338146 - Yen; Yung-Sung ;   et al.
2017-11-23
Method of forming interconnect structures by self-aligned approach
Grant 9,824,922 - Chen , et al. November 21, 2
2017-11-21
Method of forming interconnect structures by self-aligned approach
Grant 9,659,821 - Chen , et al. May 23, 2
2017-05-23
Method Of Fabricating Semiconductor Device With Reduced Trench Distortions
App 20160358788 - Yen; Yung-Sung ;   et al.
2016-12-08
Method Of Fabricating Semiconductor Device
App 20160240430 - Yen; Yung-Sung ;   et al.
2016-08-18
Method of fabricating semiconductor device with reduced trench distortions
Grant 9,418,868 - Yen , et al. August 16, 2
2016-08-16
Method of fabricating semiconductor device
Grant 9,412,649 - Yen , et al. August 9, 2
2016-08-09

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