Yu; Shifeng
Patent Applications and Registrations
Patent applications and USPTO patent grants for Yu; Shifeng.The latest application filed is for "system and method for integrated circuit calibration".
- Yu; Shifeng - Santa Clara CA
- Yu; Shifeng - Fremont CA US
| Patent | Date |
|---|---|
| Oxide stress reduction for a cascode stack circuit Grant 8,860,497 - Pattnayak , et al. October 14, 2 | 2014-10-14 |
| System and method for integrated circuit calibration Grant 8,793,091 - Ku , et al. July 29, 2 | 2014-07-29 |
| System And Method For Integrated Circuit Calibration App 20090259425 - Ku; Ting ; et al. | 2009-10-15 |
| System And Method For Input/output Control During Power Down Mode App 20090259864 - Li; Alan ; et al. | 2009-10-15 |
| Input/output buffer for wide supply voltage range Grant 7,570,088 - Ku , et al. August 4, 2 | 2009-08-04 |
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