loadpatents
name:-0.026297092437744
name:-0.029891967773438
name:-0.0036308765411377
Yu; Roy Patent Filings

Yu; Roy

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yu; Roy.The latest application filed is for "nanostructure featuring nano-topography with optimized electrical & biochemical properties".

Company Profile
2.23.19
  • Yu; Roy - Poughkeepsie NY
  • Yu; Roy - Wappingers Falls NY
  • Yu; Roy - Wappinger Falls NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Nanostructure Featuring Nano-topography With Optimized Electrical & Biochemical Properties
App 20200176262 - Camagong; Cristina ;   et al.
2020-06-04
Nanostructure Featuring Nano-topography With Optimized Electrical And Biochemical Properties
App 20200173953 - Camagong; Cristina ;   et al.
2020-06-04
Chip and wafer integration process using vertical connections
Grant 7,564,118 - Pogge , et al. July 21, 2
2009-07-21
Chip And Wafer Integration Process Using Vertical Connections
App 20080230891 - Pogge; H. Bernhard ;   et al.
2008-09-25
Chip and wafer integration process using vertical connections
Grant 7,388,277 - Pogge , et al. June 17, 2
2008-06-17
Three-dimensional device fabrication method
Grant 7,354,798 - Pogge , et al. April 8, 2
2008-04-08
Integrated Electronic Chip And Interconnect Device And Process For Making The Same
App 20070252287 - Pogge; H. Bernhard ;   et al.
2007-11-01
Integrated electronic chip and interconnect device and process for making the same
App 20060278998 - Pogge; H. Bernhard ;   et al.
2006-12-14
Three-dimensional integrated CMOS-MEMS device and process for making the same
Grant 7,071,031 - Pogge , et al. July 4, 2
2006-07-04
Three-dimensional device fabrication method
App 20060121690 - Pogge; H Bernhard ;   et al.
2006-06-08
Process for making fine pitch connections between devices and structure made by the process
Grant 7,049,697 - Pogge , et al. May 23, 2
2006-05-23
Thin film transfer join process and multilevel thin film module
Grant 6,998,327 - Danielson , et al. February 14, 2
2006-02-14
Process for making fine pitch connections between devices and structure made by the process
App 20050173800 - Pogge, H. Bernhard ;   et al.
2005-08-11
Chip and wafer integration process using vertical connections
App 20050121711 - Pogge, H. Bernhard ;   et al.
2005-06-09
Integrated Electronic Chip And Interconnect Device And Process For Making The Same
App 20050056943 - Pogge, H. Bernhard ;   et al.
2005-03-17
Method Of Fabricating Integrated Electronic Chip With An Interconnect Device
App 20050056942 - Pogge, H. Bernhard ;   et al.
2005-03-17
Method of fabricating integrated electronic chip with an interconnect device
Grant 6,864,165 - Pogge , et al. March 8, 2
2005-03-08
Chip and wafer integration process using vertical connections
Grant 6,856,025 - Pogge , et al. February 15, 2
2005-02-15
Three-dimensional integrated CMOS-MEMS device and process for making the same
Grant 6,835,589 - Pogge , et al. December 28, 2
2004-12-28
Three-dimensional integrated CMOS-MEMS device and process for making the same
App 20040097002 - Pogge, H. Bernhard ;   et al.
2004-05-20
Three-dimensional integrated CMOS-MEMS device and process for making the same
App 20040097004 - Pogge, H. Bernhard ;   et al.
2004-05-20
Thin film transfer join process and multilevel thin film module
App 20040097078 - Danielson, Jeffrey B. ;   et al.
2004-05-20
Process for making fine pitch connections between devices and structure made by the process
Grant 6,737,297 - Pogge , et al. May 18, 2
2004-05-18
Process for forming a multi-level thin-film electronic packaging structure
Grant 6,678,949 - Prasad , et al. January 20, 2
2004-01-20
Chip and wafer integration process using vertical connections
App 20030215984 - Pogge, H. Bernhard ;   et al.
2003-11-20
Fabrication of a hybrid integrated circuit device including an optoelectronic chip
Grant 6,640,021 - Pogge , et al. October 28, 2
2003-10-28
Chip and wafer integration process using vertical connections
Grant 6,599,778 - Pogge , et al. July 29, 2
2003-07-29
Thin film attachment to laminate using a dendritic interconnection
Grant 6,600,224 - Farquhar , et al. July 29, 2
2003-07-29
Chip And Wafer Integration Process Using Vertical Connections
App 20030111733 - Pogge, H. Bernhard ;   et al.
2003-06-19
Fabrication of a hybrid integrated circuit device including an optoelectronic chip
App 20030108269 - Pogge, H. Bernhard ;   et al.
2003-06-12
Process for making fine pitch connections between devices and structure made by the process
App 20030015788 - Pogge, H. Bernhard ;   et al.
2003-01-23
Process for making fine pitch connections between devices and structure made by the process
Grant 6,444,560 - Pogge , et al. September 3, 2
2002-09-03
Column for module component
Grant 6,331,731 - Kelly , et al. December 18, 2
2001-12-18
Process for forming a multi-level thin-film electronic packaging structure
App 20010037565 - Prasad, Chandrika ;   et al.
2001-11-08
Process of top-surface-metallurgy plate-up bonding and rewiring for multilayer devices
App 20010023081 - Yu, Roy ;   et al.
2001-09-20
Multi-level thin-film electronic packaging structure and related method
Grant 6,281,452 - Prasad , et al. August 28, 2
2001-08-28
Process for transferring a thin-film structure to a substrate
Grant 6,183,588 - Kelly , et al. February 6, 2
2001-02-06
Process for transferring a thin-film structure to a temporary carrier
Grant 6,143,117 - Kelly , et al. November 7, 2
2000-11-07
Apparatus for providing solder interconnections to semiconductor and electronic packaging devices
Grant 6,099,935 - Brearley , et al. August 8, 2
2000-08-08
Process for releasing a thin-film structure from a substrate
Grant 6,036,809 - Kelly , et al. March 14, 2
2000-03-14
Ball grid array by partitioned lamination process
Grant 5,735,452 - Yu , et al. April 7, 1
1998-04-07
Method for producing planar field emission structure
Grant 5,458,520 - DeMercurio , et al. October 17, 1
1995-10-17

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