loadpatents
Patent applications and USPTO patent grants for Yu; Ho Che.The latest application filed is for "integrated circuit and layout method for standard cell structures".
Patent | Date |
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Cell structures and semiconductor devices having same Grant 11,281,836 - Chang , et al. March 22, 2 | 2022-03-22 |
Integrated Circuit and Layout Method for Standard Cell Structures App 20220058330 - CHEN; Sheng-Hsiung ;   et al. | 2022-02-24 |
Integrated circuit and layout method for standard cell structures Grant 11,170,152 - Chen , et al. November 9, 2 | 2021-11-09 |
Cell Structures And Semiconductor Devices Having Same App 20210224460 - CHANG; Fong-Yuan ;   et al. | 2021-07-22 |
Semiconductor Device With Cell Region, Method Of Generating Layout Diagram And System For Same App 20210209287 - CHEN; Sheng-Hsiung ;   et al. | 2021-07-08 |
Finfet Switch App 20210159120 - Sio; Kam-Tou ;   et al. | 2021-05-27 |
Semiconductor device with cell region, method of generating layout diagram and system for same Grant 10,977,418 - Chen , et al. April 13, 2 | 2021-04-13 |
Cell structures and semiconductor devices having same Grant 10,970,450 - Chang , et al. April 6, 2 | 2021-04-06 |
FinFET switch Grant 10,937,695 - Sio , et al. March 2, 2 | 2021-03-02 |
Integrated Circuit And Layout Method For Standard Cell Structures App 20200327274 - CHEN; Sheng-Hsiung ;   et al. | 2020-10-15 |
Integrated circuit and layout method for standard cell structures Grant 10,733,352 - Chen , et al. | 2020-08-04 |
Finfet Switch App 20200118875 - Sio; Kam-Tou ;   et al. | 2020-04-16 |
Semiconductor Device With Cell Region, Method Of Generating Layout Diagram And System For Same App 20200104462 - CHEN; Sheng-Hsiung ;   et al. | 2020-04-02 |
FinFET switch Grant 10,510,599 - Sio , et al. Dec | 2019-12-17 |
Integrated Circuit And Layout Method For Standard Cell Structures App 20190155984 - CHEN; Sheng-Hsiung ;   et al. | 2019-05-23 |
Cell Structures And Semiconductor Devices Having Same App 20180150592 - CHANG; Fong-Yuan ;   et al. | 2018-05-31 |
Switch cell structure and method Grant 9,900,005 - Chen , et al. February 20, 2 | 2018-02-20 |
Switch Cell Structure and Method App 20170346485 - Chen; Chih-Liang ;   et al. | 2017-11-30 |
Finfet Switch App 20170301586 - Sio; Kam-Tou ;   et al. | 2017-10-19 |
Optimization for circuit migration Grant 9,672,315 - Lu , et al. June 6, 2 | 2017-06-06 |
Layout modification method and system Grant 9,400,866 - Lee , et al. July 26, 2 | 2016-07-26 |
Optimization for circuit migration Grant 9,275,186 - Lu , et al. March 1, 2 | 2016-03-01 |
Layout boundary method Grant 9,262,570 - Hsu , et al. February 16, 2 | 2016-02-16 |
Layout Modification Method And System App 20150363540 - LEE; Meng-Xiang ;   et al. | 2015-12-17 |
Layout modification method and system Grant 9,122,839 - Lee , et al. September 1, 2 | 2015-09-01 |
Layout Modification Method And System App 20140351784 - LEE; Meng-Xiang ;   et al. | 2014-11-27 |
Layout Boundary Method App 20140282344 - Hsu; Chin-Hsiung ;   et al. | 2014-09-18 |
Layout modification method and system Grant 8,826,195 - Lee , et al. September 2, 2 | 2014-09-02 |
Design Optimization for Circuit Migration App 20140245251 - Lu; Lee-Chung ;   et al. | 2014-08-28 |
Layout Modification Method And System App 20130326438 - LEE; Meng-Xiang ;   et al. | 2013-12-05 |
Chip-level ECO shrink Grant 8,418,117 - Chen , et al. April 9, 2 | 2013-04-09 |
Chip-Level ECO Shrink App 20110072405 - Chen; Huang-Yu ;   et al. | 2011-03-24 |
Design Optimization for Circuit Migration App 20110035717 - Lu; Lee-Chung ;   et al. | 2011-02-10 |
Analog and mixed signal IC layout system Grant 7,739,646 - Lin , et al. June 15, 2 | 2010-06-15 |
Rule-based schematic diagram generator Grant 7,386,823 - Tsai , et al. June 10, 2 | 2008-06-10 |
Analog And Mixed Signal Ic Layout System App 20080092099 - Lin; Po-Hung ;   et al. | 2008-04-17 |
Rule-based schematic diagram generator App 20070022399 - Tsai; Tian-Hau ;   et al. | 2007-01-25 |
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