| Patent | Date |
|---|
Fabrication of dual work-function metal gate structure for complementary field effect transistors
Grant 7,033,919 - Yu , et al. April 25, 2 | 2006-04-25 |
Fabrication of dual work-function metal gate structure for complementary field effect transistors
Grant 6,864,163 - Yu , et al. March 8, 2 | 2005-03-08 |
Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate
Grant 6,709,924 - Yu , et al. March 23, 2 | 2004-03-23 |
Pitch reduction using a set of offset masks
Grant 6,605,541 - Yu August 12, 2 | 2003-08-12 |
Methods to form reduced dimension bit-line isolation in the manufacture of non-volatile memory devices
Grant 6,596,591 - Yu , et al. July 22, 2 | 2003-07-22 |
Semiconductor with increased gate coupling coefficient
Grant 6,448,606 - Yu , et al. September 10, 2 | 2002-09-10 |
Controlled gate length and gate profile semiconductor device
Grant 6,433,371 - Scholer , et al. August 13, 2 | 2002-08-13 |
Recipe management database system
Grant 6,430,572 - Steffan , et al. August 6, 2 | 2002-08-06 |
Method of making vertical field effect transistor having channel length determined by the thickness of a layer of dummy material
Grant 6,387,758 - Yu , et al. May 14, 2 | 2002-05-14 |
Formation of non-volatile memory device comprised of an array of vertical field effect transistor structures
Grant 6,376,312 - Yu April 23, 2 | 2002-04-23 |
In line yield prediction using ADC determined kill ratios die health statistics and die stacking
Grant 6,338,001 - Steffan , et al. January 8, 2 | 2002-01-08 |
Global cluster pre-classification methodology
Grant 6,303,394 - Steffan , et al. October 16, 2 | 2001-10-16 |
Electroless plated semiconductor vias and channels
Grant 6,291,332 - Yu , et al. September 18, 2 | 2001-09-18 |
Automatic method to eliminate first-wafer effect
Grant 6,291,252 - Yu , et al. September 18, 2 | 2001-09-18 |
High density contacts having rectangular cross-section for dual damascene applications
Grant 6,261,960 - Yu , et al. July 17, 2 | 2001-07-17 |
Method of making a density multiplier for semiconductor device manufacturing
Grant 6,239,008 - Yu , et al. May 29, 2 | 2001-05-29 |
Self-aligned extension junction for reduced gate channel
Grant 6,204,133 - Yu , et al. March 20, 2 | 2001-03-20 |
Method for isolation of optical defect images
Grant 6,200,823 - Steffan , et al. March 13, 2 | 2001-03-13 |
Method for forming graded LDD transistor using controlled polysilicon gate profile
Grant 6,191,044 - Yu , et al. February 20, 2 | 2001-02-20 |
Scan tool recipe server
Grant 6,165,805 - Steffan , et al. December 26, 2 | 2000-12-26 |
Method to manufacture dual damascene structures by utilizing short resist spacers
Grant 6,103,616 - Yu , et al. August 15, 2 | 2000-08-15 |
Multiple chip hybrid package using bump technology
Grant 6,100,593 - Yu , et al. August 8, 2 | 2000-08-08 |
Method to selectively electroplate conductive material into trenches
Grant 6,093,647 - Yu , et al. July 25, 2 | 2000-07-25 |
Multi-chip packaging using bump technology
Grant 6,091,138 - Yu , et al. July 18, 2 | 2000-07-18 |
Universal alignment marks for semiconductor defect capture and analysis
Grant 6,084,679 - Steffan , et al. July 4, 2 | 2000-07-04 |
Dual damascene process using high selectivity boundary layers
Grant 6,025,259 - Yu , et al. February 15, 2 | 2000-02-15 |
LDD transistor using novel gate trim technique
Grant 6,013,570 - Yu , et al. January 11, 2 | 2000-01-11 |
Method to manufacture dual damascene using a phantom implant mask
Grant 5,985,753 - Yu , et al. November 16, 1 | 1999-11-16 |
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