Young; Steven P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Young; Steven P..The latest application filed is for "compute dataflow architecture".

Company Profile

2.200.50

Young; Steven P. - Boulder CO
Young; Steven P - Billerica MA
Young; Steven P. - Billerica MA US
Young; Steven P. - Abilene TX
Young, Steven P. - Bouldert CO
Young; Steven P. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Power delivery network for active-on-active stacked integrated circuits Grant 11,270,977 - Jain , et al. March 8, 2	2022-03-08
Multi-chip stacked devices Grant 11,239,203 - Gaide , et al. February 1, 2	2022-02-01
Compute Dataflow Architecture App 20210336622 - YOUNG; Steven P. ; et al.	2021-10-28
Power Delivery Network For Active-on-active Stacked Integrated Circuits App 20210143127 - JAIN; Praful ; et al.	2021-05-13
Multi-chip Stacked Devices App 20210134760 - GAIDE; Brian C. ; et al.	2021-05-06
Redundancy scheme for multi-chip stacked devices Grant 10,825,772 - Young , et al. November 3, 2	2020-11-03
Redundancy Scheme For Multi-chip Stacked Devices App 20200303311 - YOUNG; Steven P. ; et al.	2020-09-24
Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements Grant 10,715,149 - Dellinger , et al.	2020-07-14
Distributed multi-die routing in a multi-chip module Grant 9,859,896 - Gaide , et al. January 2, 2	2018-01-02
Lut cascading circuit Grant 9,602,108 - Gaide , et al. March 21, 2	2017-03-21
Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer Grant 9,509,307 - Santurkar , et al. November 29, 2	2016-11-29
Circuits for and methods of controlling power within an integrated circuit Grant 9,438,244 - Sood , et al. September 6, 2	2016-09-06
Signed multiplier circuit utilizing a uniform array of logic blocks Grant 9,411,554 - Young , et al. August 9, 2	2016-08-09
Circuits For And Methods Of Controlling Power Within An Integrated Circuit App 20160118988 - Sood; Santosh Kumar ; et al.	2016-04-28
Two gate pitch FPGA memory cell Grant 9,177,634 - Young , et al. November 3, 2	2015-11-03
Method and apparatus to reduce power segmentation overhead within an integrated circuit Grant 9,058,454 - Young , et al. June 16, 2	2015-06-16
Circuits for shifting bussed data Grant 9,002,915 - Young , et al. April 7, 2	2015-04-07
Clock network architecture Grant 8,937,491 - Gaide , et al. January 20, 2	2015-01-20
Method and apparatus for programmable device testing in stacked die applications Grant 8,933,447 - Rahman , et al. January 13, 2	2015-01-13
Self-timed single track circuit Grant 8,773,166 - Gaide , et al. July 8, 2	2014-07-08
Programmable interconnect network Grant 8,773,164 - Gaide , et al. July 8, 2	2014-07-08
Wheel cover system for a 3-wheeled motorcycle Grant 8,768,570 - Young July 1, 2	2014-07-01
Clock Network Architecture App 20140132305 - Gaide; Brian C. ; et al.	2014-05-15
Multiplier circuits with optional shift function Grant 8,706,793 - Young April 22, 2	2014-04-22
Wheel Cover System For A 3-wheeled Motorcycle App 20130320714 - Young; Steven P.	2013-12-05
Hydraulic wheel suspension system for a 3-wheeled motorcycle Grant 8,543,291 - Young September 24, 2	2013-09-24
Configuration of a multi-die integrated circuit Grant 8,536,895 - Lu , et al. September 17, 2	2013-09-17
Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same Grant 8,527,572 - Young , et al. September 3, 2	2013-09-03
Hydraulic Wheel Suspension System For A 3-wheeled Motorcycle App 20130211674 - Young; Steven P.	2013-08-15
Programmable device with dynamic DSP architecture Grant 8,495,122 - Simkins , et al. July 23, 2	2013-07-23
Error checking parity and syndrome of a block of data with relocated parity bits Grant 8,301,988 - Cory , et al. October 30, 2	2012-10-30
Hybrid integrated circuit device Grant 8,293,547 - Karp , et al. October 23, 2	2012-10-23
Error checking parity and syndrome of a block of data with relocated parity bits Grant 8,245,102 - Cory , et al. August 14, 2	2012-08-14
Programmable integrated circuit with mirrored interconnect structure Grant 8,120,382 - Bauer , et al. February 21, 2	2012-02-21
Configuration Of A Multi-die Integrated Circuit App 20120019292 - Lu; Weiguang ; et al.	2012-01-26
Configuration of a multi-die integrated circuit Grant 8,058,897 - Lu , et al. November 15, 2	2011-11-15
Clock distribution to facilitate gated clocks Grant 8,058,905 - Klein , et al. November 15, 2	2011-11-15
Programmable Integrated Circuit With Mirrored Interconnect Structure App 20110215834 - Bauer; Trevor J. ; et al.	2011-09-08
Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies Grant 8,001,511 - Bauer , et al. August 16, 2	2011-08-16
Bus-based logic blocks with optional constant input Grant 7,982,496 - Young July 19, 2	2011-07-19
Hybrid Integrated Circuit Device App 20110147949 - Karp; James ; et al.	2011-06-23
Formation of columnar application specific circuitry using a columnar programmable device Grant 7,965,102 - Bauer , et al. June 21, 2	2011-06-21
Circuits for replicating self-timed logic Grant 7,948,265 - Young , et al. May 24, 2	2011-05-24
Formation of a hybrid integrated circuit device Grant 7,919,845 - Karp , et al. April 5, 2	2011-04-05
Methods and apparatus for device-specific configuration of a programmable integrated circuit Grant 7,902,863 - Tetzlaff , et al. March 8, 2	2011-03-08
Error checking parity and syndrome of a block of data with relocated parity bits Grant 7,895,509 - Cory , et al. February 22, 2	2011-02-22
Pipelined unidirectional programmable interconnect in an integrated circuit Grant 7,759,974 - Young July 20, 2	2010-07-20
Integrated circuit having embedded differential clock tree Grant 7,759,973 - Vadi , et al. July 20, 2	2010-07-20
Cascading input structure for logic blocks in integrated circuits Grant 7,746,101 - Young June 29, 2	2010-06-29
Circuits for fanning out data in a programmable self-timed integrated circuit Grant 7,746,110 - Gaide , et al. June 29, 2	2010-06-29
Circuits for enabling feedback paths in a self-timed integrated circuit Grant 7,746,106 - Gaide , et al. June 29, 2	2010-06-29
Circuit structures utilizing multiple voltage level inputs Grant 7,746,113 - Young June 29, 2	2010-06-29
Multi-mode circuit in a self-timed integrated circuit Grant 7,746,103 - Gaide , et al. June 29, 2	2010-06-29
Dynamically controlled output multiplexer circuits in a programmable integrated circuit Grant 7,746,104 - Gaide , et al. June 29, 2	2010-06-29
Compute-centric architecture for integrated circuits Grant 7,746,108 - Young , et al. June 29, 2	2010-06-29
Merging data streams in a self-timed programmable integrated circuit Grant 7,746,105 - Gaide , et al. June 29, 2	2010-06-29
Bus-based logic blocks for self-timed integrated circuits Grant 7,746,102 - Young , et al. June 29, 2	2010-06-29
Gating logic circuits in a self-timed integrated circuit Grant 7,746,111 - Gaide , et al. June 29, 2	2010-06-29
Circuits for sharing self-timed logic Grant 7,746,109 - Young , et al. June 29, 2	2010-06-29
Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the same Grant 7,746,112 - Gaide , et al. June 29, 2	2010-06-29
Methods of initializing routing structures in integrated circuits Grant 7,743,175 - Young , et al. June 22, 2	2010-06-22
Implementing conditional statements in self-timed logic circuits Grant 7,733,123 - Young , et al. June 8, 2	2010-06-08
Characterizing circuit performance by separating device and interconnect impact on signal delay Grant 7,724,016 - Yuan , et al. May 25, 2	2010-05-25
Integrated circuits with bus-based programmable interconnect structures Grant 7,635,989 - Young December 22, 2	2009-12-22
Regional signal-distribution network for an integrated circuit Grant 7,617,472 - Bergendahl , et al. November 10, 2	2009-11-10
Integrated circuits with novel handshake logic Grant 7,605,604 - Young October 20, 2	2009-10-20
Applications of cascading DSP slices Grant 7,567,997 - Simkins , et al. July 28, 2	2009-07-28
Columnar floorplan Grant 7,557,610 - Young July 7, 2	2009-07-07
Formation of a hybrid integrated circuit device App 20090160482 - Karp; James ; et al.	2009-06-25
Structures and methods to avoiding hold time violations in a programmable logic device Grant 7,548,089 - Bauer , et al. June 16, 2	2009-06-16
Characterizing Circuit Performance By Separating Device And Interconnect Impact On Signal Delay App 20090121737 - Yuan; Xiao-Jie ; et al.	2009-05-14
Differential clock tree in an integrated circuit Grant 7,518,401 - Vadi , et al. April 14, 2	2009-04-14
Methods of providing a family of related integrated circuits of different sizes Grant 7,498,192 - Goetting , et al. March 3, 2	2009-03-03
Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit Grant 7,499,513 - Tetzlaff , et al. March 3, 2	2009-03-03
Yield-enhancing methods of providing a family of scaled integrated circuits Grant 7,491,576 - Young , et al. February 17, 2	2009-02-17
Characterizing circuit performance by separating device and interconnect impact on signal delay Grant 7,489,152 - Yuan , et al. February 10, 2	2009-02-10
Arithmetic circuit with multiplexed addend inputs Grant 7,480,690 - Simkins , et al. January 20, 2	2009-01-20
Formation of columnar application specific circuitry using a columnar programmable logic device Grant 7,478,359 - Bauer , et al. January 13, 2	2009-01-13
Programmable logic device with cascading DSP slices Grant 7,472,155 - Simkins , et al. December 30, 2	2008-12-30
Mathematical circuit with dynamic rounding Grant 7,467,177 - Simkins , et al. December 16, 2	2008-12-16
Programmable logic device with pipelined DSP slices Grant 7,467,175 - Simkins , et al. December 16, 2	2008-12-16
Single event upset in SRAM cells in FPGAs with high resistivity gate structures Grant 7,452,765 - Voogel , et al. November 18, 2	2008-11-18
Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies Grant 7,451,421 - Bauer , et al. November 11, 2	2008-11-11
Error checking parity and syndrome of a block of data with relocated parity bits Grant 7,426,678 - Cory , et al. September 16, 2	2008-09-16
Programmable gate array and embedded circuitry initialization and processing Grant 7,420,392 - Schultz , et al. September 2, 2	2008-09-02
Programmable logic device having an embedded differential clock tree Grant 7,414,430 - Vadi , et al. August 19, 2	2008-08-19
Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes Grant 7,402,443 - Pang , et al. July 22, 2	2008-07-22
Interconnect driver circuits for dynamic logic Grant 7,382,157 - Young , et al. June 3, 2	2008-06-03
Dadoing System App 20080121311 - Young; Steven P.	2008-05-29
Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure Grant 7,375,552 - Young , et al. May 20, 2	2008-05-20
Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Grant 7,376,000 - Voogel , et al. May 20, 2	2008-05-20
Differential clock tree in an integrated circuit Grant 7,372,299 - Vadi , et al. May 13, 2	2008-05-13
Regional signal-distribution network for an integrated circuit Grant 7,353,487 - Bergendahl , et al. April 1, 2	2008-04-01
Multi-product die configurable as two or more programmable integrated circuits of different logic capacities Grant 7,345,507 - Young , et al. March 18, 2	2008-03-18
Double data rate flip-flop Grant 7,317,773 - Young , et al. January 8, 2	2008-01-08
Method and system for configuring an integrated circuit Grant 7,314,174 - Vadi , et al. January 1, 2	2008-01-01
Structures and methods for avoiding hold time violations in a programmable logic device Grant 7,312,631 - Bauer , et al. December 25, 2	2007-12-25
Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Grant 7,301,796 - Voogel , et al. November 27, 2	2007-11-27
Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability Grant 7,286,382 - Vadi , et al. October 23, 2	2007-10-23
Integrated circuit with programmable routing structure including straight and diagonal interconnect lines Grant 7,279,929 - Young October 9, 2	2007-10-09
Integrated circuit with programmable routing structure including diagonal interconnect lines Grant 7,276,934 - Young October 2, 2	2007-10-02
Efficient tile layout for a programmable logic device Grant 7,274,214 - Young September 25, 2	2007-09-25
Programmable logic block with carry chains providing lookahead functions of different lengths Grant 7,268,587 - Pham , et al. September 11, 2	2007-09-11
Programmable lookup table with dual input and output terminals in RAM mode Grant 7,265,576 - Kondapalli , et al. September 4, 2	2007-09-04
Programmable logic block providing carry chain with programmable initialization values Grant 7,256,612 - Young , et al. August 14, 2	2007-08-14
Integrated circuit providing direct access to multi-directional interconnect lines in a general interconnect structure Grant 7,253,658 - Young August 7, 2	2007-08-07
Circuit for and method of implementing a content addressable memory in a programmable logic device Grant 7,248,491 - Ching , et al. July 24, 2	2007-07-24
Memory device and method of transferring data in memory device Grant 7,242,633 - Ching , et al. July 10, 2	2007-07-10
Efficient tile layout for a programmable logic device Grant 7,221,186 - Young May 22, 2	2007-05-22
Integrated circuit having fast interconnect paths between memory elements and carry logic Grant 7,218,143 - Young May 15, 2	2007-05-15
Programmable integrated circuit providing efficient implementations of arithmetic functions Grant 7,218,139 - Young , et al. May 15, 2	2007-05-15
Integrated circuit having fast interconnect paths between carry chain multiplexers and lookup tables Grant 7,218,140 - Young May 15, 2	2007-05-15
Programmable lookup table with dual input and output terminals in shift register mode Grant 7,215,138 - Kondapalli , et al. May 8, 2	2007-05-08
Programmable integrated circuit providing efficient implementations of wide logic functions Grant 7,205,790 - Young April 17, 2	2007-04-17
Integrated circuit having a programmable input structure with bounce capability Grant 7,202,698 - Bauer , et al. April 10, 2	2007-04-10
Gate valve App 20070075288 - Matte; StephenR ; et al.	2007-04-05
Integrated circuit interconnect structure having reduced coupling between interconnect lines Grant 7,199,610 - Young , et al. April 3, 2	2007-04-03
Integrated circuit having a programmable input structure with optional fanout capability Grant 7,196,543 - Young , et al. March 27, 2	2007-03-27
Programmable logic block having lookup table with partial output signal driving carry multiplexer Grant 7,193,433 - Young March 20, 2	2007-03-20
Columnar architecture Grant 7,187,200 - Young March 6, 2	2007-03-06
Columnar floorplan App 20070035330 - Young; Steven P.	2007-02-15
Differential clock tree in an integrated circuit App 20070013428 - Vadi; Vasisht Mantra ; et al.	2007-01-18
Programmable logic device having an embedded differential clock tree App 20060290402 - Vadi; Vasisht Mantra ; et al.	2006-12-28
Differential clock tree in an integrated circuit App 20060290403 - Vadi; Vasisht Mantra ; et al.	2006-12-28
Characterizing circuit performance by separating device and interconnect impact on signal delay App 20060267618 - Yuan; Xiao-Jie ; et al.	2006-11-30
Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability Grant 7,142,442 - Vadi , et al. November 28, 2	2006-11-28
Columnar floorplan Grant 7,132,851 - Young November 7, 2	2006-11-07
Differential clock tree in an integrated circuit Grant 7,129,765 - Vadi , et al. October 31, 2	2006-10-31
Programmable logic device having an embedded differential clock tree Grant 7,126,406 - Vadi , et al. October 24, 2	2006-10-24
Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Grant 7,110,281 - Voogel , et al. September 19, 2	2006-09-19
Characterizing circuit performance by separating device and interconnect impact on signal delay Grant 7,109,734 - Yuan , et al. September 19, 2	2006-09-19
Programmable multi-chip module Grant 7,095,253 - Young August 22, 2	2006-08-22
Structures and methods for selectively applying a well bias to portions of a programmable device Grant 7,089,527 - Hart , et al. August 8, 2	2006-08-08
Six-input look-up table and associated memory control circuitry for use in a field programmable gate array Grant 7,075,332 - Young , et al. July 11, 2	2006-07-11
Clock multiplexing system Grant 7,071,756 - Vadi , et al. July 4, 2	2006-07-04
Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit Grant 7,068,072 - New , et al. June 27, 2	2006-06-27
PLD memory cells utilizing metal-to-metal capacitors to selectively reduce susceptibility to single event upsets Grant 7,064,574 - Voogel , et al. June 20, 2	2006-06-20
Six-input look-up table for use in a field programmable gate array Grant 7,061,271 - Young , et al. June 13, 2	2006-06-13
Large crossbar switch implemented in FPGA Grant 7,057,413 - Young , et al. June 6, 2	2006-06-06
PLD lookup table including transistors of more than one oxide thickness Grant 7,053,654 - Young , et al. May 30, 2	2006-05-30
Single event upset in SRAM cells in FPGAs with high resistivity gate structures Grant 6,982,451 - Voogel , et al. January 3, 2	2006-01-03
Glitchless dynamic multiplexer with synchronous and asynchronous controls Grant 6,975,145 - Vadi , et al. December 13, 2	2005-12-13
Differential clock tree in an integrated circuit App 20050242865 - Vadi, Vasisht Mantra ; et al.	2005-11-03
Programmable logic device having an embedded differential clock tree App 20050242866 - Vadi, Vasisht Mantra ; et al.	2005-11-03
Integrated circuit multiplexer including transistors of more than one oxide thickness Grant 6,949,951 - Young , et al. September 27, 2	2005-09-27
Structures and methods of testing interconnect structures in programmable logic devices Grant 6,933,747 - Bauer , et al. August 23, 2	2005-08-23
Characterizing circuit performance by separating device and interconnect impact on signal delay App 20050149777 - Yuan, Xiao-Jie ; et al.	2005-07-07
Programmable logic device with dynamic DSP architecture App 20050144210 - Simkins, James M. ; et al.	2005-06-30
Arithmetic circuit with multiplexed addend inputs App 20050144216 - Simkins, James M. ; et al.	2005-06-30
Mathematical circuit with dynamic rounding App 20050144213 - Simkins, James M. ; et al.	2005-06-30
Applications of cascading DSP slices App 20050144215 - Simkins, James M. ; et al.	2005-06-30
Programmable logic device with cascading DSP slices App 20050144212 - Simkins, James M. ; et al.	2005-06-30
Programmable logic device with pipelined DSP slices App 20050144211 - Simkins, James M. ; et al.	2005-06-30
Windowing circuit for aligning data and clock signals Grant 6,864,715 - Bauer , et al. March 8, 2	2005-03-08
Programmable gate array and embedded circuitry initialization and processing App 20050040850 - Schultz, David P. ; et al.	2005-02-24
Carry logic design having simplified timing modeling for a field programmable gate array Grant 6,847,228 - Crotty , et al. January 25, 2	2005-01-25
Columnar floorplan App 20050007147 - Young, Steven P.	2005-01-13
Columnar architecture App 20050007155 - Young, Steven P.	2005-01-13
Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit App 20040268286 - New, Bernard J. ; et al.	2004-12-30
Double data rate flip-flop App 20040239365 - Young, Steven P. ; et al.	2004-12-02
Structures and methods for selectively applying a well bias to portions of a programmable device App 20040216074 - Hart, Michael J. ; et al.	2004-10-28
Programmable gate array having interconnecting logic to support embedded fixed logic circuitry Grant 6,798,239 - Douglass , et al. September 28, 2	2004-09-28
Methods for aligning data and clock signals Grant 6,798,241 - Bauer , et al. September 28, 2	2004-09-28
Structures and methods for selectively applying a well bias to portions of a programmable device Grant 6,777,978 - Hart , et al. August 17, 2	2004-08-17
Double data rate flip-flop Grant 6,777,980 - Young , et al. August 17, 2	2004-08-17
Digital phase shifter Grant 6,775,342 - Young , et al. August 10, 2	2004-08-10
PLD lookup table including transistors of more than one oxide thickness Grant 6,768,338 - Young , et al. July 27, 2	2004-07-27
Integrated circuit multiplexer including transistors of more than one oxide thickness Grant 6,768,335 - Young , et al. July 27, 2	2004-07-27
Large crossbar switch implemented in FPGA Grant 6,759,869 - Young , et al. July 6, 2	2004-07-06
Configurable logic block with and gate for efficient multiplication in FPGAS Grant 6,708,191 - Chapman , et al. March 16, 2	2004-03-16
Structures and methods for selectively applying a well bias to portions of a programmable device App 20040025135 - Hart, Michael J. ; et al.	2004-02-05
FPGA lookup table with high speed read decorder Grant 6,621,296 - Carberry , et al. September 16, 2	2003-09-16
Structures and methods for selectively applying a well bias to portions of a programmable device Grant 6,621,325 - Hart , et al. September 16, 2	2003-09-16
Gate valve with delayed retraction of counter plate Grant 6,612,546 - Young , et al. September 2, 2	2003-09-02
Configurable logic block for PLD with logic gate for combining output with another configurable logic block Grant 6,603,332 - Kaviani , et al. August 5, 2	2003-08-05
Double data rate flip-flop App 20030112032 - Young, Steven P. ; et al.	2003-06-19
Method and apparatus for incorporating a multiplier into an FPGA Grant 6,573,749 - New , et al. June 3, 2	2003-06-03
FPGA lookup table with high speed read decoder App 20030071653 - Carberry, Richard A. ; et al.	2003-04-17
Programmable gate array having interconnecting logic to support embedded fixed logic circuitry App 20030062922 - Douglass, Stephen M. ; et al.	2003-04-03
Structures and methods for selectively applying a well bias to portions of a programmable device App 20030053335 - Hart, Michael J. ; et al.	2003-03-20
FPGA lookup table with speed read decoder Grant 6,529,040 - Carberry , et al. March 4, 2	2003-03-04
Double data rate flip-flop Grant 6,525,565 - Young , et al. February 25, 2	2003-02-25
Architecture and method for partially reconfiguring an FPGA Grant 6,526,557 - Young , et al. February 25, 2	2003-02-25
User configurable on-chip memory system Grant 6,522,167 - Ansari , et al. February 18, 2	2003-02-18
Gate valve with delayed retraction of counter plate App 20030025098 - Young, Steven P. ; et al.	2003-02-06
Double data rate flip-flop App 20020175704 - Young, Steven P. ; et al.	2002-11-28
Configurable logic block with and gate for efficient multiplication in FPGAS App 20020178431 - Chapman, Kenneth D. ; et al.	2002-11-28
Clock routing circuit with fast glitchless switching Grant 6,472,909 - Young October 29, 2	2002-10-29
Interconnect structure for a programmable logic device Grant 6,448,808 - Young , et al. September 10, 2	2002-09-10
Clock multiplexer circuit with glitchless switching Grant 6,429,698 - Young August 6, 2	2002-08-06
Configurable logic block with AND gate for efficient multiplication in FPGAS Grant 6,427,156 - Chapman , et al. July 30, 2	2002-07-30
Configurable logic block for PLD with logic gate for combining output with another configurable logic block App 20020079921 - Kaviani, Alireza S. ; et al.	2002-06-27
Expandable interconnect structure for FPGAS Grant 6,396,303 - Young May 28, 2	2002-05-28
Method and apparatus for incorporating a multiplier into an FPGA App 20020057104 - New, Bernard J. ; et al.	2002-05-16
Block RAM having multiple configurable write modes for use in a field programmable gate array Grant 6,373,779 - Pang , et al. April 16, 2	2002-04-16
FPGA lookup table with dual ended writes for ram and shift register modes Grant 6,373,279 - Bauer , et al. April 16, 2	2002-04-16
Multiplexer for implementing logic functions in a programmable logic device Grant 6,362,648 - New , et al. March 26, 2	2002-03-26
Method and apparatus for incorporating a multiplier into an FPGA Grant 6,362,650 - New , et al. March 26, 2	2002-03-26
Block RAM with configurable data width and parity for use in a field programmable gate array Grant 6,346,825 - Pang , et al. February 12, 2	2002-02-12
Interconnect structure for a programmable logic device App 20020008541 - Young, Steven P. ; et al.	2002-01-24
FPGA with a plurality of input reference voltage levels App 20020005735 - Goetting, F. Erich ; et al.	2002-01-17
FPGA architecture with wide function multiplexers Grant 6,323,682 - Bauer , et al. November 27, 2	2001-11-27
FPGA architecture with dual-port deep look-up table RAMS Grant 6,297,665 - Bauer , et al. October 2, 2	2001-10-02
FPGA with a plurality of input reference voltage levels Grant 6,294,930 - Goetting , et al. September 25, 2	2001-09-25
FPGA architecture with deep look-up table RAMs Grant 6,288,568 - Bauer , et al. September 11, 2	2001-09-11
Block RAM with reset to user selected value Grant 6,282,127 - Pang , et al. August 28, 2	2001-08-28
Method and circuit for operating programmable logic devices during power-up and stand-by modes Grant 6,278,290 - Young August 21, 2	2001-08-21
FIFO in FPGA having logic elements that include cascadable shift registers Grant 6,262,597 - Bauer , et al. July 17, 2	2001-07-17
Interconnect structure for a programmable logic device App 20010007428 - Young, Steven P. ; et al.	2001-07-12
Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA Grant 6,255,848 - Schultz , et al. July 3, 2	2001-07-03
Method and system for measuring signal propagation delays using ring oscillators Grant 6,219,305 - Patrie , et al. April 17, 2	2001-04-17
Structure and method for generating a clock enable signal in a PLD Grant 6,218,864 - Young , et al. April 17, 2	2001-04-17
Clock-gating circuit for reducing power consumption Grant 6,204,695 - Alfke , et al. March 20, 2	2001-03-20
Input/output interconnect circuit for FPGAs Grant 6,204,689 - Percey , et al. March 20, 2	2001-03-20
Wide logic gate implemented in an FPGA configurable logic element Grant 6,201,410 - New , et al. March 13, 2	2001-03-13
FPGA configurable by two types of bitstreams Grant 6,201,406 - Iwanczuk , et al. March 13, 2	2001-03-13
Method for generating an FPGA two turn routing structure with lane changing and minimum diffusion area Grant 6,163,167 - Young December 19, 2	2000-12-19
Structure and method for loading narrow frames of data from a wide input bus Grant 6,154,048 - Iwanczuk , et al. November 28, 2	2000-11-28
FPGA Architecture using multiplexers that incorporate a logic gate Grant 6,144,220 - Young November 7, 2	2000-11-07
Structure and method for loading wide frames of data from a narrow input bus Grant 6,137,307 - Iwanczuk , et al. October 24, 2	2000-10-24
Configurable logic element with ability to evaluate wide logic functions Grant 6,124,731 - Young , et al. September 26, 2	2000-09-26
FPGA CLE with two independent carry chains Grant 6,107,827 - Young , et al. August 22, 2	2000-08-22
Interconnect structure for FPGA with configurable delay locked loop Grant 6,107,826 - Young , et al. August 22, 2	2000-08-22
Multiplexer array with shifted input traces Grant 6,097,210 - Iwanczuk , et al. August 1, 2	2000-08-01
Programmable power reduction in a clock-distribution circuit Grant 6,072,348 - New , et al. June 6, 2	2000-06-06
FPGA having fast configuration memory data readback Grant 6,069,489 - Iwanczuk , et al. May 30, 2	2000-05-30
Configurable logic element with ability to evaluate five and six input functions Grant 6,051,992 - Young , et al. April 18, 2	2000-04-18
FPGA with a plurality of I/O voltage levels Grant 6,049,227 - Goetting , et al. April 11, 2	2000-04-11
Efficient multiplexer structure for use in FPGA logic blocks Grant 6,020,776 - Young February 1, 2	2000-02-01
Configurable logic element with fast feedback paths Grant 5,963,050 - Young , et al. October 5, 1	1999-10-05
High speed bus with tree structure for selecting bus driver Grant 5,936,424 - Young , et al. August 10, 1	1999-08-10
FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines Grant 5,933,023 - Young August 3, 1	1999-08-03
FPGA repeatable interconnect structure with hierarchical interconnect lines Grant 5,914,616 - Young , et al. June 22, 1	1999-06-22
FPGA interconnect structure with high-speed high fanout capability Grant 5,907,248 - Bauer , et al. May 25, 1	1999-05-25
FPGA with a plurality of I/O voltage levels Grant 5,877,632 - Goetting , et al. March 2, 1	1999-03-02
FPGA memory element programmably triggered on both clock edges Grant 5,844,844 - Bauer , et al. December 1, 1	1998-12-01
FPGA two turn routing structure with lane changing and minimum diffusion area Grant 5,828,230 - Young October 27, 1	1998-10-27
FPGA one turn routing structure and method using minimum diffusion area Grant 5,818,730 - Young October 6, 1	1998-10-06