Young; Jay T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Young; Jay T..The latest application filed is for "method of selecting routing resources in a multi-chip integrated circuit device".

Company Profile

2.18.2

Young; Jay T. - Louisville CO
Young; Jay T. - Loisville CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements Grant 10,715,149 - Dellinger , et al.	2020-07-14
Method of selecting routing resources in a multi-chip integrated circuit device Grant 10,467,373 - Young No	2019-11-05
Method Of Selecting Routing Resources In A Multi-chip Integrated Circuit Device App 20190258767 - Young; Jay T.	2019-08-22
Methods of prioritizing routing resources to generate and evaluate test designs in programmable logic devices Grant 8,418,221 - Young , et al. April 9, 2	2013-04-09
Generating a module interface for partial reconfiguration design flows Grant 8,332,788 - Young , et al. December 11, 2	2012-12-11
Generating a module interface for partial reconfiguration design flows Grant 7,941,777 - Young , et al. May 10, 2	2011-05-10
Method and apparatus for providing secure intellectual property cores for a programmable logic device Grant 7,890,917 - Young , et al. February 15, 2	2011-02-15
Method and apparatus for generating an area constraint for a module in a programmable logic device Grant 7,673,272 - Young March 2, 2	2010-03-02
Method and apparatus for modular circuit design for a programmable logic device Grant 7,600,210 - Mason , et al. October 6, 2	2009-10-06
Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements Grant 7,509,617 - Young March 24, 2	2009-03-24
Method and apparatus for reducing the number of test designs for device testing Grant 7,480,842 - Young , et al. January 20, 2	2009-01-20
Reducing design execution run time bit stream size for device testing Grant 7,299,430 - McEwen , et al. November 20, 2	2007-11-20
Methods of routing programmable logic devices to minimize programming time Grant 7,249,335 - Young , et al. July 24, 2	2007-07-24
Routing with frame awareness to minimize device programming time and test cost Grant 7,149,997 - Young , et al. December 12, 2	2006-12-12
Methods of routing programmable logic devices to minimize programming time Grant 7,143,384 - Young , et al. November 28, 2	2006-11-28
Methods of generating test designs for testing specific routing resources in programmable logic devices Grant 7,058,919 - Young , et al. June 6, 2	2006-06-06
Methods of resource optimization in programmable logic devices to reduce test time Grant 6,944,809 - Lai , et al. September 13, 2	2005-09-13
Dedicated resource placement enhancement Grant 6,760,899 - Young , et al. July 6, 2	2004-07-06
Methods of resource optimization in programmable logic devices to reduce test time App 20040030975 - Lai, Andrew W. ; et al.	2004-02-12

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