Young; Gene F.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Young; Gene F..The latest application filed is for "interleaved card/riser connection assembly for compact card integration".

Company Profile

3.10.5

Young; Gene F. - Lexington SC
Young; Gene F. - Portland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuit card with coherent interconnect Grant 11,251,576 - Blevins , et al. February 15, 2	2022-02-15
Interleaved card/riser connection assembly for compact card integration Grant 10,958,003 - Young March 23, 2	2021-03-23
Interleaved Card/riser Connection Assembly For Compact Card Integration App 20210044043 - YOUNG; Gene F.	2021-02-11
Computer Chassis With Parallel Backplanes App 20190121402 - Puligundla; Sudeep ; et al.	2019-04-25
Circuit Card With Coherent Interconnect App 20190044293 - Blevins; Dirk ; et al.	2019-02-07
Module With Laterally Translatable Component Platform App 20170215297 - Young; Gene F. ; et al.	2017-07-27
High density serverlets utilizing high speed data bus App 20020075860 - Young, Gene F.	2002-06-20
Directory-based coherency system for maintaining coherency in a dual-ported memory system Grant 6,078,997 - Young , et al. June 20, 2	2000-06-20
Dual-ported memory controller which maintains cache coherency using a memory line status table Grant 5,991,819 - Young November 23, 1	1999-11-23
Method and apparatus for caching state information within a directory-based coherency memory system Grant 5,848,434 - Young , et al. December 8, 1	1998-12-08
Method for reducing the number of coherency cycles within a directory-based cache coherency memory system uitilizing a memory state cache Grant 5,809,536 - Young , et al. September 15, 1	1998-09-15
System for preventing an unselected controller from transferring data via a first bus while concurrently permitting it to transfer data via a second bus Grant 5,454,082 - Walrath , et al. September 26, 1	1995-09-26
Retry scheme for controlling transactions between two busses Grant 5,418,914 - Heil , et al. May 23, 1	1995-05-23
Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces Grant 5,359,715 - Heil , et al. October 25, 1	1994-10-25
Method and apparatus for transferring data within a computer system Grant 5,269,005 - Heil , et al. December 7, 1	1993-12-07

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.