loadpatents
name:-0.0070550441741943
name:-0.0072619915008545
name:-0.00042510032653809
Yoshizawa; Keiji Patent Filings

Yoshizawa; Keiji

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yoshizawa; Keiji.The latest application filed is for "wiring substrate and semiconductor device".

Company Profile
0.6.6
  • Yoshizawa; Keiji - Nagano JP
  • YOSHIZAWA; KEIJI - NAGANO-SHI JP
  • Yoshizawa; Keiji - Futtsu JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Wiring substrate and semiconductor device
Grant 9,899,304 - Imafuji , et al. February 20, 2
2018-02-20
Wiring Substrate And Semiconductor Device
App 20170186677 - IMAFUJI; KEI ;   et al.
2017-06-29
Wiring Substrate And Semiconductor Device
App 20140301058 - SUNOHARA; Satoshi ;   et al.
2014-10-09
Patterning method and computer readable medium therefor
Grant 7,495,745 - Yoshizawa , et al. February 24, 2
2009-02-24
Patterning method and computer readable medium therefor
App 20080123070 - Yoshizawa; Keiji ;   et al.
2008-05-29
Sizing processing system and computer program for the same
Grant 7,099,806 - Yoshizawa August 29, 2
2006-08-29
Method of efficiently converting-to-array and compressing data in a process for converting mask patterns of a LSI
Grant 7,085,417 - Yoshizawa August 1, 2
2006-08-01
Reduction processing method and computer readable storage medium having program stored thereon for causing computer to execute the method
Grant 6,957,176 - Yoshizawa October 18, 2
2005-10-18
Sizing processing system and computer program for the same
App 20020181796 - Yoshizawa, Keiji
2002-12-05
Method of efficiently converting-to-array and compressing data in a process for converting mask patterns of a LSI
App 20020105524 - Yoshizawa, Keiji
2002-08-08
Reduction processing method and computer readable storage medium having program stored thereon for causing computer to execute the method
App 20010055033 - Yoshizawa, Keiji
2001-12-27
Laminate for insulation protection of circuit boards
Grant 5,601,905 - Watanabe , et al. February 11, 1
1997-02-11

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed