Yoshimura; Masayoshi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yoshimura; Masayoshi.The latest application filed is for "semiconductor integrated circuit and testing method for the same".

Company Profile

0.12.7

Yoshimura; Masayoshi - Kyoto JP
Yoshimura; Masayoshi - Maebashi JP
Yoshimura; Masayoshi - Nishitama JP
Yoshimura; Masayoshi - Tokyo JA
Yoshimura; Masayoshi - Hamura JA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device Grant 7,348,595 - Takeoka , et al. March 25, 2	2008-03-25
Semiconductor integrated circuit and testing method for the same App 20070250284 - Takeoka; Sadami ; et al.	2007-10-25
Semiconductor integrated circuit and testing method for the same Grant 7,197,725 - Takeoka , et al. March 27, 2	2007-03-27
Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device Grant 7,171,600 - Takeoka , et al. January 30, 2	2007-01-30
Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device Grant 7,032,196 - Takeoka , et al. April 18, 2	2006-04-18
Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device App 20040195672 - Takeoka, Sadami ; et al.	2004-10-07
Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device App 20040197941 - Takeoka, Sadami ; et al.	2004-10-07
Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device App 20040199840 - Takeoka, Sadami ; et al.	2004-10-07
Semiconductor device having a device for testing the semiconductor Grant 6,734,549 - Takeoka , et al. May 11, 2	2004-05-11
Method of design for testability, method of design for integrated circuits and integrated circuits Grant 6,708,315 - Hosokawa , et al. March 16, 2	2004-03-16
Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device App 20030025191 - Takeoka, Sadami ; et al.	2003-02-06
Semiconductor integrated circuit and testing method for the same App 20030021464 - Takeoka, Sadami ; et al.	2003-01-30
Method of design for testability, method of design for integrated circuits and integrated circuits App 20020129322 - Hosokawa, Toshinori ; et al.	2002-09-12
Level conversion circuitry for a semiconductor integrated circuit Grant 5,245,224 - Suzuki , et al. * September 14, 1	1993-09-14
Level conversion circuitry for a semiconductor integrated circuit utilizing bis CMOS circuit elements Grant 4,689,503 - Suzuki , et al. August 25, 1	1987-08-25
High-breakdown-voltage resistance element for integrated circuit with a plurality of multilayer, overlapping electrodes Grant 4,423,433 - Imaizumi , et al. December 27, 1	1983-12-27
Single in-line high power resin-packaged semiconductor device having an improved heat dissipator Grant 4,095,253 - Yoshimura , et al. June 13, 1	1978-06-13
Etching method for flattening a silicon substrate utilizing an anisotropic alkali etchant Grant 4,056,413 - Yoshimura November 1, 1	1977-11-01
Transistor with base/emitter encirclement configuration Grant 4,024,568 - Yoshimura May 17, 1	1977-05-17

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