loadpatents
Patent applications and USPTO patent grants for Yoshida; Shuji.The latest application filed is for "welding state inspection method".
Patent | Date |
---|---|
Welding state inspection method Grant 10,466,204 - Kawamoto , et al. No | 2019-11-05 |
Pyrometer Grant D862,256 - Hasegawa , et al. O | 2019-10-08 |
Welding State Inspection Method App 20150369779 - KAWAMOTO; Koichi ;   et al. | 2015-12-24 |
Processes for producing succinic acid Grant 9,035,095 - Mori , et al. May 19, 2 | 2015-05-19 |
Processes For Producing Succinic Acid App 20130018206 - MORI; Yoshiaki ;   et al. | 2013-01-17 |
Mass spectrometry unit Grant 8,138,473 - Nakajima , et al. March 20, 2 | 2012-03-20 |
Mass Spectrometry Unit App 20100213363 - Nakajima; Toyoaki ;   et al. | 2010-08-26 |
Driving method and input method, for touch panel App 20080001928 - Yoshida; Shuji | 2008-01-03 |
Character recognizing method and character input method for touch panel App 20080001927 - Yoshida; Shuji | 2008-01-03 |
Semiconductor device including an external oscillation circuit Grant 7,135,939 - Koike , et al. November 14, 2 | 2006-11-14 |
Semiconductor device App 20050128013 - Koike, Yoshihiko ;   et al. | 2005-06-16 |
LSI layout method and apparatus for cell arrangement in which timing is prioritized Grant 6,857,107 - Nagasaka , et al. February 15, 2 | 2005-02-15 |
Logic circuit for fast carry/borrow Grant 6,781,412 - Yoshida , et al. August 24, 2 | 2004-08-24 |
Method and apparatus for automatic wiring design between block circuits of integrated circuit Grant 6,760,897 - Arakawa , et al. July 6, 2 | 2004-07-06 |
Semiconductor device Grant 6,621,328 - Koike , et al. September 16, 2 | 2003-09-16 |
Cleaning gas for semiconductor production equipment App 20030056388 - Ohno, Hiromoto ;   et al. | 2003-03-27 |
Method and apparatus for automatic wiring design between block circuits of integrated circuit App 20030054619 - Arakawa, Toshio ;   et al. | 2003-03-20 |
Semiconductor device App 20030038673 - Koike, Yoshihiko ;   et al. | 2003-02-27 |
LSI layout method and apparatus for cell arrangement in which timing is prioritized App 20030023938 - Nagasaka, Mitsuaki ;   et al. | 2003-01-30 |
Logic circuit for fast carry/borrow App 20020188641 - Yoshida, Shuji ;   et al. | 2002-12-12 |
Inductor recognition method, layout inspection method, computer readable recording medium in which a layout inspection program is recorded and process for a semiconductor device App 20020110936 - Wada, Yoshiki ;   et al. | 2002-08-15 |
Overglaze colors for pottery Grant 5,262,363 - Yoshida , et al. November 16, 1 | 1993-11-16 |
Communication terminal device Grant 5,099,512 - Shigami , et al. March 24, 1 | 1992-03-24 |
Optical reading apparatus Grant 4,907,091 - Yoshida , et al. March 6, 1 | 1990-03-06 |
Process for producing copper through-hole printed circuit board Grant 4,622,097 - Tsukagoshi , et al. November 11, 1 | 1986-11-11 |
Threaded Tube Joint Structure For A Casing Grant 3,850,461 - Fujioka , et al. November 26, 1 | 1974-11-26 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.