Yorav; Karen
Patent Applications and Registrations
Patent applications and USPTO patent grants for Yorav; Karen.The latest application filed is for "system level test generation using dnn translation from unit level test".
- Yorav; Karen - Haifa IL
| Patent | Date |
|---|---|
| System level test generation using DNN translation from unit level test Grant 10,915,436 - Copty , et al. February 9, 2 | 2021-02-09 |
| System Level Test Generation Using Dnn Translation From Unit Level Test App 20200183816 - COPTY; FADY ; et al. | 2020-06-11 |
| Verification of UML state machines Grant 9,454,382 - Adler , et al. September 27, 2 | 2016-09-27 |
| Verification Of Uml State Machines App 20150106781 - Adler; Oshri ; et al. | 2015-04-16 |
| Dominant-state-based coverage metric Grant 8,856,755 - Chockler , et al. October 7, 2 | 2014-10-07 |
| Specification properties creation for a visual model of a system App 20140214396 - Adir; Allon ; et al. | 2014-07-31 |
| Dominant-state-based Coverage Metric App 20140215445 - Chockler; Hana ; et al. | 2014-07-31 |
| Automatic parity checking identification Grant 8,589,841 - Arbel , et al. November 19, 2 | 2013-11-19 |
| Automatic Parity Checking Identification App 20130268906 - Arbel; Eli ; et al. | 2013-10-10 |
| SAT-based synthesis of a clock gating function Grant 8,296,256 - Arbel , et al. October 23, 2 | 2012-10-23 |
| Sat-based Synthesis Of A Clock Gating Function App 20110093431 - Arbel; Eli ; et al. | 2011-04-21 |
| Method and system to verify a circuit design by verifying consistency between two different language representations of a circuit design Grant 7,225,417 - Clarke , et al. May 29, 2 | 2007-05-29 |
| Method And System To Verify A Circuit Design App 20050071147 - Clarke, Edmund M. ; et al. | 2005-03-31 |
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