YONG; Wae Chet

Patent Applications and Registrations

Patent applications and USPTO patent grants for YONG; Wae Chet.The latest application filed is for "stacked transistor chip package with source coupling".

Company Profile

2.14.14

YONG; Wae Chet - Malacca MY
Yong; Wae Chet - Melaka MY
Yong; Wae Chet - Semabok MY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stacked Transistor Chip Package With Source Coupling App 20220122906 - YUFEREV; Sergey ; et al.	2022-04-21
Chip to Chip Interconnect in Encapsulant of Molded Semiconductor Package App 20210391298 - Saw; Khay Chwan ; et al.	2021-12-16
Chip to chip interconnect in encapsulant of molded semiconductor package Grant 11,133,281 - Saw , et al. September 28, 2	2021-09-28
Encapsulated leadless package having an at least partially exposed interior sidewall of a chip carrier Grant 10,978,378 - Bemmerl , et al. April 13, 2	2021-04-13
Chip to Chip Interconnect in Encapsulant of Molded Semiconductor Package App 20200321276 - Saw; Khay Chwan ; et al.	2020-10-08
Encapsulated Leadless Package Having an at Least Partially Exposed Interior Sidewall of a Chip Carrier App 20190189542 - Bemmerl; Thomas ; et al.	2019-06-20
Method of fabricating a semiconductor package with mold lock opening Grant 8,466,009 - Goller , et al. June 18, 2	2013-06-18
Method of fabricating a semiconductor device having a resin with warpage compensated structures Grant 8,377,753 - Heng , et al. February 19, 2	2013-02-19
Integrated Semiconductor Outline Package App 20120162924 - Job Doraisamy; Stanley ; et al.	2012-06-28
Electronic component and a method of fabricating an electronic component Grant 8,207,601 - Low , et al. June 26, 2	2012-06-26
Integrated semiconductor outline package Grant 8,169,069 - Job Doraisamy , et al. May 1, 2	2012-05-01
Method of Fabricating A Semiconductor Device Having A Resin With Warpage Compensated Structures App 20120058606 - Heng; Chai Wei ; et al.	2012-03-08
Semiconductor device including isolation layer Grant 8,110,906 - Mahler , et al. February 7, 2	2012-02-07
Semiconductor devices having a resin with warpage compensated surfaces Grant 8,067,841 - Heng , et al. November 29, 2	2011-11-29
Semiconductor device Grant 7,821,141 - Yong , et al. October 26, 2	2010-10-26
Method Of Fabricating A Semiconductor Package With Mold Lock Opening App 20100227436 - Goller; Bernd ; et al.	2010-09-09
Semiconductor component having maximized bonding areas of electrically conductive members connected to semiconductor device and connected to leadframe and method of producing Grant 7,791,182 - Yong , et al. September 7, 2	2010-09-07
Semiconductor package with mold lock vent Grant 7,732,937 - Goller , et al. June 8, 2	2010-06-08
Method of forming component package Grant 7,723,165 - Tong , et al. May 25, 2	2010-05-25
Semiconductor Package With Mold Lock Vent App 20090224382 - Goller; Bernd ; et al.	2009-09-10
Semiconductor Device App 20090212417 - Yong; Wae Chet ; et al.	2009-08-27
Semiconductor Device App 20090212446 - Heng; Chai Wei ; et al.	2009-08-27
Semiconductor Component And Method Of Producing App 20090045493 - Yong; Wae Chet ; et al.	2009-02-19
Electronic Component and a Method of Fabricating an Electronic Component App 20090001536 - Low; Khai Huat Jeffrey ; et al.	2009-01-01
Semiconductor Device Including Isolation Layer App 20080173992 - Mahler; Joachim ; et al.	2008-07-24
Method of Forming Component Package App 20080160677 - TONG; Soon Hock ; et al.	2008-07-03

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