loadpatents
name:-0.024461030960083
name:-0.030860900878906
name:-0.0014598369598389
Yip; Sherman H. Patent Filings

Yip; Sherman H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yip; Sherman H..The latest application filed is for "reducing pipeline restart penalty".

Company Profile
0.27.21
  • Yip; Sherman H. - San Francisco CA
  • Yip; Sherman H. - Sunnyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Precise data return handling in speculative processors
Grant 8,984,264 - Karlsson , et al. March 17, 2
2015-03-17
Anti-prefetch instruction
Grant 8,732,438 - Caprioli , et al. May 20, 2
2014-05-20
Checkpoint allocation in a speculative processor
Grant 8,688,963 - Chaudhry , et al. April 1, 2
2014-04-01
Space-efficient mechanism to support additional scouting in a processor using checkpoints
Grant 8,572,356 - Yip , et al. October 29, 2
2013-10-29
Pseudo-LRU cache line replacement for a high-speed cache
Grant 8,364,900 - Caprioli , et al. January 29, 2
2013-01-29
Hardware transactional memory acceleration through multiple failure recovery
Grant 8,327,188 - Karlsson , et al. December 4, 2
2012-12-04
Facilitating transactional execution in a processor that supports simultaneous speculative threading
Grant 8,316,366 - Yip , et al. November 20, 2
2012-11-20
Merging checkpoints in an execute-ahead processor
Grant 8,181,002 - Yip , et al. May 15, 2
2012-05-15
Method and apparatus for determining cache storage locations based on latency requirements
Grant 8,065,485 - Levinsky , et al. November 22, 2
2011-11-22
Reducing Pipeline Restart Penalty
App 20110264862 - Karlsson; Martin ;   et al.
2011-10-27
Checkpoint Allocation In A Speculative Processor
App 20110264898 - Chaudhry; Shailender ;   et al.
2011-10-27
Method and apparatus for improving transactional memory commit latency
Grant 8,041,900 - Caprioli , et al. October 18, 2
2011-10-18
Limiting Speculative Instruction Fetching In A Processor
App 20110179254 - Yip; Sherman H. ;   et al.
2011-07-21
Precise Data Return Handling In Speculative Processors
App 20110179258 - Karlsson; Martin R. ;   et al.
2011-07-21
Space-efficient Mechanism To Support Additional Scouting In A Processor Using Checkpoints
App 20110167243 - Yip; Sherman H. ;   et al.
2011-07-07
Hardware Transactional Memory Acceleration Through Multiple Failure Recovery
App 20110119528 - Karlsson; Martin R. ;   et al.
2011-05-19
Method And Apparatus For Determining Cache Storage Locations Based On Latency Requirements
App 20100299482 - Levinsky; Gideon N. ;   et al.
2010-11-25
Method and apparatus for measuring performance during speculative execution
Grant 7,757,068 - Caprioli , et al. July 13, 2
2010-07-13
Method and apparatus for counting instructions during speculative execution
Grant 7,716,457 - Caprioli , et al. May 11, 2
2010-05-11
Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency
Grant 7,650,487 - Chaudhry , et al. January 19, 2
2010-01-19
Avoiding live-lock in a processor that supports speculative execution
Grant 7,634,639 - Chaudhry , et al. December 15, 2
2009-12-15
Method and apparatus for reporting failure conditions during transactional execution
Grant 7,617,421 - Caprioli , et al. November 10, 2
2009-11-10
Mechanism for hardware tracking of return address after tail call elimination of return-type instruction
Grant 7,610,474 - Caprioli , et al. October 27, 2
2009-10-27
Anti-prefetch Instruction
App 20090265532 - Caprioli; Paul ;   et al.
2009-10-22
Facilitating Transactional Execution In A Processor That Supports Simultaneous Speculative Threading
App 20090254905 - Yip; Sherman H. ;   et al.
2009-10-08
Pseudo-lru Cache Line Replacement For A High-speed Cache
App 20090204761 - Caprioli; Paul ;   et al.
2009-08-13
Method And Apparatus For Improving Transactional Memory Commit Latency
App 20090182956 - Caprioli; Paul ;   et al.
2009-07-16
Method and structure for pipelining of SIMD conditional moves
Grant 7,480,787 - Caprioli , et al. January 20, 2
2009-01-20
Circuitry and method for accessing an associative cache with parallel determination of data and data availability
Grant 7,461,208 - Caprioli , et al. December 2, 2
2008-12-02
Method and apparatus for sampling instructions on a processor that supports speculative execution
Grant 7,418,581 - Chaudhry , et al. August 26, 2
2008-08-26
Method and apparatus for measuring performance during speculative execution
App 20080172548 - Caprioli; Paul ;   et al.
2008-07-17
Method and apparatus for counting instructions during speculative execution
App 20080172549 - Caprioli; Paul ;   et al.
2008-07-17
Method and apparatus for reporting failure conditions during transactional execution
App 20080126883 - Caprioli; Paul ;   et al.
2008-05-29
Method for graphically displaying hardware performance simulators
Grant 7,331,039 - Yip , et al. February 12, 2
2008-02-12
Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency
Grant 7,293,163 - Caprioli , et al. November 6, 2
2007-11-06
Method and apparatus for sampling instructions on a processor that supports speculative execution
App 20070226472 - Chaudhry; Shailender ;   et al.
2007-09-27
Technique for executing selected instructions in order
App 20070226465 - Chaudhry; Shailender ;   et al.
2007-09-27
Avoiding register RAW hazards when returning from speculative execution
Grant 7,257,700 - Chaudhry , et al. August 14, 2
2007-08-14
Mechanism for hardware tracking of return address after tail call elimination of return-type instruction
App 20070130451 - Caprioli; Paul ;   et al.
2007-06-07
Avoiding live-lock in a processor that supports speculative execution
App 20070050601 - Chaudhry; Shailender ;   et al.
2007-03-01
Branch prediction accuracy in a processor that supports speculative execution
App 20060168432 - Caprioli; Paul ;   et al.
2006-07-27
Avoiding register RAW hazards when returning from speculative execution
App 20050273580 - Chaudhry, Shailender ;   et al.
2005-12-08
Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor
App 20050210223 - Caprioli, Paul ;   et al.
2005-09-22

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed