Yi; Yanhua
Patent Applications and Registrations
Patent applications and USPTO patent grants for Yi; Yanhua.The latest application filed is for "machine learning delay estimation for emulation systems".
- Yi; Yanhua - Cupertino CA
- Yi; Yanhua - Allentown PA
| Patent | Date |
|---|---|
| Machine Learning Delay Estimation For Emulation Systems App 20220187367 - Yi; Yanhua ; et al. | 2022-06-16 |
| Clock placement for programmable logic devices Grant 9,672,307 - Chen , et al. June 6, 2 | 2017-06-06 |
| Clock Placement For Programmable Logic Devices App 20160321385 - Chen; Chih-Chung ; et al. | 2016-11-03 |
| Bus-based clock to out path optimization Grant 9,390,220 - Yi , et al. July 12, 2 | 2016-07-12 |
| Holdtime correction using input/output block delay Grant 9,330,217 - Yi , et al. May 3, 2 | 2016-05-03 |
| Bus-based Clock To Out Path Optimization App 20160026746 - Yi; Yanhua ; et al. | 2016-01-28 |
| Clock To Out Path Optimization App 20160026745 - Yi; Yanhua ; et al. | 2016-01-28 |
| Holdtime Correction Using Input/output Block Delay App 20150370941 - Yi; Yanhua ; et al. | 2015-12-24 |
| Multi-priority placement for configuring programmable logic devices Grant 8,181,139 - Chen , et al. May 15, 2 | 2012-05-15 |
| Scan chain systems and methods for programmable logic devices Grant 7,757,198 - Zhao , et al. July 13, 2 | 2010-07-13 |
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