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Combining write buffer with dynamically adjustable flush metrics
Grant 8,566,528 - Bannon , et al. October 22, 2 | 2013-10-22 |
Combining Write Buffer with Dynamically Adjustable Flush Metrics
App 20130103906 - Bannon; Peter J. ; et al. | 2013-04-25 |
Combining write buffer with dynamically adjustable flush metrics
Grant 8,352,685 - Bannon , et al. January 8, 2 | 2013-01-08 |
Replay reduction for power saving
Grant 8,255,670 - Chang , et al. August 28, 2 | 2012-08-28 |
Misalignment Predictor
App 20120110392 - Yeh; Tse-Yu ; et al. | 2012-05-03 |
L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down
Grant 8,171,326 - Keller , et al. May 1, 2 | 2012-05-01 |
Misalignment predictor
Grant 8,171,240 - Yeh , et al. May 1, 2 | 2012-05-01 |
Combining Write Buffer with Dynamically Adjustable Flush Metrics
App 20120047332 - Bannon; Peter J. ; et al. | 2012-02-23 |
Misalignment predictor
Grant 8,117,404 - Yeh , et al. February 14, 2 | 2012-02-14 |
Efficient encoding for detecting load dependency on store with misalignment
Grant 7,996,646 - Yeh , et al. August 9, 2 | 2011-08-09 |
Fast L1 Flush Mechanism
App 20100235670 - Keller; James B. ; et al. | 2010-09-16 |
L1 cache flush when processor is entering low power mode
Grant 7,752,474 - Keller , et al. July 6, 2 | 2010-07-06 |
Efficient Encoding for Detecting Load Dependency on Store with Misalignment
App 20100169619 - Yeh; Tse-yu ; et al. | 2010-07-01 |
Efficient encoding for detecting load dependency on store with misalignment
Grant 7,721,066 - Yeh , et al. May 18, 2 | 2010-05-18 |
Replay Reduction for Power Saving
App 20100064120 - Chang; Po-Yung ; et al. | 2010-03-11 |
Replay reduction for power saving
Grant 7,647,518 - Chang , et al. January 12, 2 | 2010-01-12 |
Efficient Encoding for Detecting Load Dependency on Store with Misalignment
App 20080307173 - Yeh; Tse-yu ; et al. | 2008-12-11 |
Uncacheable load merging
App 20080086594 - Chang; Po-Yung ; et al. | 2008-04-10 |
Replay reduction for power saving
App 20080086622 - Chang; Po-Yung ; et al. | 2008-04-10 |
Fast L1 flush mechanism
App 20080077813 - Keller; James B. ; et al. | 2008-03-27 |
Inhibiting of a co-issuing instruction in a processor having different pipeline lengths
Grant 7,269,714 - Yeh , et al. September 11, 2 | 2007-09-11 |
Power consumption reduction in a pipeline by stalling instruction issue on a load miss
Grant 7,203,817 - Yeh April 10, 2 | 2007-04-10 |
Misalignment predictor
App 20070038847 - Yeh; Tse-Yu ; et al. | 2007-02-15 |
Mechanism for processing speculative LL and SC instructions in a pipelined processor
Grant 7,162,613 - Yeh , et al. January 9, 2 | 2007-01-09 |
Limiting performance in an integrated circuit to meet export restrictions
Grant 7,100,064 - Rogenmoser , et al. August 29, 2 | 2006-08-29 |
Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard
Grant 6,976,152 - Yeh , et al. December 13, 2 | 2005-12-13 |
Mechanism for processing speculative LL and SC instructions in a pipelined processor
App 20050154862 - Yeh, Tse-Yu ; et al. | 2005-07-14 |
Scoreboarding mechanism in a pipeline that includes replays and redirects
App 20050149698 - Yeh, Tse-Yu ; et al. | 2005-07-07 |
Mechanism for processing speclative LL and SC instructions in a pipelined processor
Grant 6,877,085 - Yeh , et al. April 5, 2 | 2005-04-05 |
Method for processing branch operations
App 20050066153 - Sharangpani, Harshvardhan ; et al. | 2005-03-24 |
Microprocessor having a branch predictor using speculative branch registers
Grant 6,871,275 - Poplingher , et al. March 22, 2 | 2005-03-22 |
Limiting performance in an integrated circuit to meet export restrictions
App 20030225999 - Rogenmoser, Robert ; et al. | 2003-12-04 |
Predicate controlled software pipelined loop processing with prediction of predicate writing and value prediction for use in subsequent iteration
Grant 6,629,238 - Arora , et al. September 30, 2 | 2003-09-30 |
Method for processing branch operations
Grant 6,611,910 - Sharangpani , et al. August 26, 2 | 2003-08-26 |
Mechanism for processing speclative LL and SC instructions in a pipelined processor
App 20030105943 - Yeh, Tse-Yu ; et al. | 2003-06-05 |
Power consumption reduction mechanism for pipeline stalls
App 20030061470 - Yeh, Tse-Yu | 2003-03-27 |
Issue and retirement mechanism in processor having different pipeline lenghths
App 20030061465 - Yeh, Tse-Yu ; et al. | 2003-03-27 |
Scoreboarding mechanism in a pipeline that includes replays and redirects
App 20030061467 - Yeh, Tse-Yu ; et al. | 2003-03-27 |
Method and apparatus for predicting loop exit branches
Grant 6,438,682 - Morris , et al. August 20, 2 | 2002-08-20 |
Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time
Grant 6,430,674 - Trivedi , et al. August 6, 2 | 2002-08-06 |
Optimized branch predictions for strongly predicted compiler branches
Grant 6,427,206 - Yeh , et al. July 30, 2 | 2002-07-30 |
Method For Processing Branch Operations
App 20020095566 - SHARANGPANI, HARSHVARDHAN ; et al. | 2002-07-18 |
Method And Apparatus For Predicting Loop Exit Branches
App 20020083310 - MORRIS, DALE ; et al. | 2002-06-27 |
Apparatus and method for cycle accounting in microprocessors
Grant 6,353,805 - Zahir , et al. March 5, 2 | 2002-03-05 |
Method And Apparatus For Branch Prediction Using First And Second Level Branch Prediction Tables
App 20010047467 - YEH, TSE-YU ; et al. | 2001-11-29 |
Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions
Grant 6,304,960 - Yeh , et al. October 16, 2 | 2001-10-16 |
Decentralized exception processing system
Grant 6,282,636 - Yeh , et al. August 28, 2 | 2001-08-28 |
Return address predictor that uses branch instructions to track a last valid return address
Grant 6,253,315 - Yeh June 26, 2 | 2001-06-26 |
System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions
Grant 6,240,510 - Yeh , et al. May 29, 2 | 2001-05-29 |
Instruction template for efficient processing clustered branch instructions
Grant 6,237,077 - Sharangpani , et al. May 22, 2 | 2001-05-22 |
Method and apparatus for performing early branch prediction in a microprocessor
Grant 6,185,676 - Poplingher , et al. February 6, 2 | 2001-02-06 |
Processor and instruction set with predict instructions
Grant 6,092,188 - Corwin , et al. July 18, 2 | 2000-07-18 |
High-performance processor with streaming buffer that facilitates prefetching of instructions
Grant 6,012,134 - McInerney , et al. January 4, 2 | 2000-01-04 |
Dynamic branch prediction for branch instructions with multiple targets
Grant 5,903,750 - Yeh , et al. May 11, 1 | 1999-05-11 |
Method and apparatus for generating branch predictions for multiple branch instructions indexed by a single instruction pointer
Grant 5,805,878 - Rahman , et al. September 8, 1 | 1998-09-08 |
Method and apparatus for performing reads of related data from a set-associative cache memory
Grant 5,802,602 - Rahman , et al. September 1, 1 | 1998-09-01 |
Instruction prefetch mechanism utilizing a branch predict instruction
Grant 5,742,804 - Yeh , et al. April 21, 1 | 1998-04-21 |
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