Yeh; Ping-Chin
Patent Applications and Registrations
Patent applications and USPTO patent grants for Yeh; Ping-Chin.The latest application filed is for "method and design of low sheet resistance meol resistors".
- Yeh; Ping-Chin - San Jose CA
| Patent | Date |
|---|---|
| IC die with dummy structures Grant 11,114,344 - Lin , et al. September 7, 2 | 2021-09-07 |
| Implantation for etch stop liner Grant 11,107,696 - Chang , et al. August 31, 2 | 2021-08-31 |
| In-die transistor characterization in an IC Grant 10,379,155 - Yeh , et al. A | 2019-08-13 |
| Method and design of low sheet resistance MEOL resistors Grant 10,103,139 - Chong , et al. October 16, 2 | 2018-10-16 |
| Method And Design Of Low Sheet Resistance Meol Resistors App 20170012041 - Chong; Nui ; et al. | 2017-01-12 |
| In-die Transistor Characterization In An Ic App 20160097805 - Yeh; Ping-Chin ; et al. | 2016-04-07 |
| Integrated circuit with stress inserts Grant 8,350,253 - Zhu , et al. January 8, 2 | 2013-01-08 |
| Semiconductor device and method for making the same Grant 8,329,568 - Ahn , et al. December 11, 2 | 2012-12-11 |
| Method and structure for controlling floating body effects Grant 7,211,473 - Pelella , et al. May 1, 2 | 2007-05-01 |
| Doped spacer liner for improved transistor performance Grant 6,583,016 - Wei , et al. June 24, 2 | 2003-06-24 |
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