Yee; Rashelle
Patent Applications and Registrations
Patent applications and USPTO patent grants for Yee; Rashelle.The latest application filed is for "warpage mitigation in printed circuit board assemblies".
- Yee; Rashelle - Puyallup WA
- Yee; Rashelle - Dupont WA US
| Patent | Date |
|---|---|
| Integrated circuit packages with temperature sensor traces Grant 10,260,961 - Ferguson , et al. | 2019-04-16 |
| Warpage mitigation in printed circuit board assemblies Grant 10,178,763 - Yee , et al. J | 2019-01-08 |
| Semiconductor package alignment frame for local reflow Grant 9,991,223 - Aoki , et al. June 5, 2 | 2018-06-05 |
| Integrated Circuit Packages With Temperature Sensor Traces App 20170176260 - Ferguson; Shelby ; et al. | 2017-06-22 |
| Integrated Circuit Package Support Structures App 20170178994 - Hui; Michael ; et al. | 2017-06-22 |
| Warpage Mitigation In Printed Circuit Board Assemblies App 20170181271 - Yee; Rashelle ; et al. | 2017-06-22 |
| Bulk Solder Removal On Processor Packaging App 20170179066 - Aoki; Russell S. ; et al. | 2017-06-22 |
| Semiconductor Package Alignment Frame For Local Reflow App 20170179067 - AOKI; RUSSELL S. ; et al. | 2017-06-22 |
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