Yee; Gin S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yee; Gin S..The latest application filed is for "non-invasive on-chip power measurement technique".

Company Profile

0.17.14

Yee; Gin S. - Mountain View CA
Yee; Gin S. - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Non-invasive on-chip power measurement technique Grant 11,215,664 - Yun , et al. January 4, 2	2022-01-04
Non-Invasive On-Chip Power Measurement Technique App 20210396805 - Yun; Ke ; et al.	2021-12-23
Circuit and method for high impedance input/output termination in shut off mode and for negative signal swing Grant 7,663,398 - Lee , et al. February 16, 2	2010-02-16
IC analog debugging and calibration thereof Grant 7,203,613 - Yee , et al. April 10, 2	2007-04-10
Compensation technique to mitigate aging effects in integrated circuit components Grant 7,129,800 - Gauthier , et al. October 31, 2	2006-10-31
Embedded integrated circuit aging sensor system Grant 7,054,787 - Gauthier , et al. May 30, 2	2006-05-30
Method for synchronizing clock and data signals Grant 6,993,103 - Greenhill , et al. January 31, 2	2006-01-31
On-chip temperature measurement technique Grant 6,934,652 - Gauthier , et al. August 23, 2	2005-08-23
Compensation technique to mitigate aging effects in integrated circuit components App 20050168255 - Gauthier, Claude R. ; et al.	2005-08-04
On-chip temperature measurement technique App 20050114061 - Gauthier, Claude R. ; et al.	2005-05-26
On-die thermal monitoring technique Grant 6,814,485 - Gauthier , et al. November 9, 2	2004-11-09
Clock frequency multiplier Grant 6,815,991 - Yee , et al. November 9, 2	2004-11-09
Negative bias temperature instability correction technique for delay locked loop and phase locked loop bias generators Grant 6,812,758 - Gauthier , et al. November 2, 2	2004-11-02
Variation reduction technique for charge pump transistor aging Grant 6,812,755 - Yee , et al. November 2, 2	2004-11-02
Single edge-triggered flip-flop design with asynchronous programmable reset App 20040187086 - Trivedi, Pradeep R. ; et al.	2004-09-23
Negative Bias Temperature Instability Correction Technique For Delay Locked Loop And Phase Locked Loop Bias Generators App 20040155696 - Gauthier, Claude R. ; et al.	2004-08-12
Embedded integrated circuit aging sensor System App 20040148111 - Gauthier, Claude R. ; et al.	2004-07-29
On-die thermal monitoring technique App 20040146086 - Gauthier, Claude R. ; et al.	2004-07-29
Variation reduction technique for charge pump transistor aging App 20040145396 - Yee, Gin S. ; et al.	2004-07-29
Clock frequency multiplier App 20040135607 - Yee, Gin S. ; et al.	2004-07-15
Dual edge-triggered flip-flop design with asynchronous programmable reset Grant 6,720,813 - Yee , et al. April 13, 2	2004-04-13
Deskewing global clock skew using localized DLLs Grant 6,686,785 - Liu , et al. February 3, 2	2004-02-03
Measuring skew using on-chip sampling Grant 6,662,126 - Liu , et al. December 9, 2	2003-12-09
Method for synchronizing clock and data signals App 20030076909 - Greenhill, David J. ; et al.	2003-04-24
Deskewing global clock skew using localized DLLs App 20030071669 - Liu, Dean ; et al.	2003-04-17
Measuring skew using on-chip sampling App 20030036862 - Liu, Dean ; et al.	2003-02-20
Reducing clock skew by power supply isolation App 20030037271 - Liu, Dean ; et al.	2003-02-20
Automated shielding algorithm for dynamic circuits Grant 6,510,545 - Yee , et al. January 21, 2	2003-01-21
Stretching, shortening, and/or removing a clock cycle App 20020149411 - Yee, Gin S.	2002-10-17
Clock divider for analysis of all clock edges Grant 6,441,656 - Yee , et al. August 27, 2	2002-08-27
Dual rail dynamic flip-flop with single evaluation path Grant 6,265,923 - Amir , et al. July 24, 2	2001-07-24

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