Yee; Gin
Patent Applications and Registrations
Patent applications and USPTO patent grants for Yee; Gin.The latest application filed is for "chip to chip interface with scalable bandwidth".
- Yee; Gin - Mountain View CA
- Yee; Gin - Sunnyvale CA
| Patent | Date |
|---|---|
| Chip to chip interface with scalable bandwidth Grant 11,023,403 - Savoj , et al. June 1, 2 | 2021-06-01 |
| Chip To Chip Interface With Scalable Bandwidth App 20200183874 - Savoj; Jafar ; et al. | 2020-06-11 |
| Chip to chip interface with scalable bandwidth Grant 10,521,391 - Savoj , et al. Dec | 2019-12-31 |
| Method for reducing lock time in a closed loop clock signal generator Grant 9,838,025 - Deng , et al. December 5, 2 | 2017-12-05 |
| Bit-deskewing IO method and system Grant 7,688,925 - Lee , et al. March 30, 2 | 2010-03-30 |
| Bit-deskewing IO method and system App 20070036020 - Lee; Edward ; et al. | 2007-02-15 |
| Region-based voltage drop budgets for low-power design Grant 6,976,235 - Bobba , et al. December 13, 2 | 2005-12-13 |
| Accuracy of timing analysis using region-based voltage drop budgets Grant 6,971,079 - Yee , et al. November 29, 2 | 2005-11-29 |
| Duty cycle corrector Grant 6,882,196 - Yee , et al. April 19, 2 | 2005-04-19 |
| Region-based voltage drop budgets for low-power design App 20040054979 - Bobba, Sudhakar ; et al. | 2004-03-18 |
| Accuracy of timing analysis using region-based voltage drop budgets App 20040054975 - Yee, Gin ; et al. | 2004-03-18 |
| Clock detect indicator Grant 6,707,320 - Trivedi , et al. March 16, 2 | 2004-03-16 |
| Duty cycle corrector App 20040012428 - Yee, Gin ; et al. | 2004-01-22 |
| Frequency multiplier design Grant 6,642,756 - Yee , et al. November 4, 2 | 2003-11-04 |
| Clock grid skew reduction technique using biasable delay drivers App 20030163750 - Trivedi, Pradeep ; et al. | 2003-08-28 |
| Clock detect indicator App 20030102899 - Trivedi, Pradeep ; et al. | 2003-06-05 |
| Lock detect indicator for a phase locked loop App 20030098720 - Trivedi, Pradeep ; et al. | 2003-05-29 |
| Clock grid skew reduction using a wire tree architecture App 20030101423 - Thorp, Tyler ; et al. | 2003-05-29 |
| Method of high-performance CMOS design Grant 6,549,038 - Sechen , et al. April 15, 2 | 2003-04-15 |
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