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Patent applications and USPTO patent grants for Yee; Fanchieh.The latest application filed is for "layout quality gauge for integrated circuit design".
Patent | Date |
---|---|
Layout quality gauge for integrated circuit design Grant 8,020,120 - Heng , et al. September 13, 2 | 2011-09-13 |
Layout Quality Gauge for Integrated Circuit Design App 20090089726 - Heng; Fook-Luen ;   et al. | 2009-04-02 |
Distributed DC voltage generator for system on chip Grant 6,803,805 - Wang , et al. October 12, 2 | 2004-10-12 |
Distributed DC voltage generator for system on chip App 20040169546 - Wang, Li-Kong ;   et al. | 2004-09-02 |
Distributed DC voltage generator for system on chip App 20030189460 - Wang, Li-Kong ;   et al. | 2003-10-09 |
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