Yeap; Gary K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yeap; Gary K..The latest application filed is for "methodology using fin-fet transistors".

Company Profile

1.14.8

Yeap; Gary K. - Fremont CA
Yeap; Gary K. - San Jose CA
Yeap; Gary K. - Gilbert AZ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methodology using Fin-FET transistors Grant 10,922,467 - Liu , et al. February 16, 2	2021-02-16
Methodology using Fin-FET transistors Grant 10,817,636 - Liu , et al. October 27, 2	2020-10-27
Methodology Using Fin-fet Transistors App 20190332737 - Liu; Bohai ; et al.	2019-10-31
Methodology Using Fin-fet Transistors App 20160125116 - LIU; Bohai ; et al.	2016-05-05
Standard cell placement technique for double patterning technology Grant 8,726,215 - Lee , et al. May 13, 2	2014-05-13
Two-chip co-design and co-optimization in three-dimensional integrated circuit net assignment Grant 8,392,870 - Zhang , et al. March 5, 2	2013-03-05
Standard Cell Placement Technique For Double Patterning Technology App 20130036397 - Lee; John Jung ; et al.	2013-02-07
Two-Chip Co-Design And Co-Optimization In Three-Dimensional Integrated Circuit Net Assignment App 20120198409 - Zhang; Yifan ; et al.	2012-08-02
Design-for-test-aware hierarchical design planning Grant 7,937,677 - Chien , et al. May 3, 2	2011-05-03
Design-For-Test-Aware Hierarchical Design Planning App 20090288045 - Chien; Hung-Chun ; et al.	2009-11-19
Placement method for integrated circuit design using topo-clustering Grant 6,961,916 - Sarrafzadeh , et al. November 1, 2	2005-11-01
Placement method for integrated circuit design using topo-clustering App 20020138816 - Sarrafzadeh, Majid ; et al.	2002-09-26
Placement method for integrated circuit design using topo-clustering Grant 6,442,743 - Sarrafzadeh , et al. August 27, 2	2002-08-27
System and method for concurrent placement of gates and associated wiring Grant 6,385,760 - Pileggi , et al. May 7, 2	2002-05-07
System And Method For Concurrent Placement Of Gates And Associated Wiring App 20010047507 - PILEGGI, LAWRENCE ; et al.	2001-11-29
Method for design optimization using logical and physical information Grant 6,286,128 - Pileggi , et al. September 4, 2	2001-09-04
Method for logic optimization for improving timing and congestion during placement in integrated circuit design Grant 6,192,508 - Malik , et al. February 20, 2	2001-02-20
Method for encoding a state machine Grant 5,825,644 - Yeap October 20, 1	1998-10-20
Method of generating power vectors for cell power dissipation simulation Grant 5,673,420 - Reyes , et al. September 30, 1	1997-09-30

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