Ye; Dehong
Patent Applications and Registrations
Patent applications and USPTO patent grants for Ye; Dehong.The latest application filed is for "method of fabricating 3-dimensional fan-out structure".
- Ye; Dehong - Tianjin CN
| Patent | Date |
|---|---|
| Method of fabricating 3-dimensional fan-out structure Grant 10,283,477 - Gao , et al. | 2019-05-07 |
| Method Of Fabricating 3-dimensional Fan-out Structure App 20170200701 - Gao; Wei ; et al. | 2017-07-13 |
| Die edge seal employing low-K dielectric material Grant 9,406,625 - Wang , et al. August 2, 2 | 2016-08-02 |
| Exposed pad integrated circuit package with mold lock Grant 9,362,211 - Gao , et al. June 7, 2 | 2016-06-07 |
| Die Edge Seal Employing Low-k Dielectric Material App 20150371957 - Wang; Zhijie ; et al. | 2015-12-24 |
| Backside Metallization Patterns For Integrated Circuits App 20150235969 - Zhang; Hanmin ; et al. | 2015-08-20 |
| Semiconductor devices and methods of assembling same Grant 8,735,223 - Gao , et al. May 27, 2 | 2014-05-27 |
| Semiconductor Devices And Methods Of Assembling Same App 20130056861 - Gao; Wei ; et al. | 2013-03-07 |
| Semiconductor Device And Method Of Packaging Same App 20130020689 - Mei; Penglin ; et al. | 2013-01-24 |
| Method Of Assembling Semiconductor Device App 20120326288 - Huang; Meiquan ; et al. | 2012-12-27 |
| Packaging process to create wettable lead flank during board assembly Grant 8,329,509 - Gong , et al. December 11, 2 | 2012-12-11 |
| Dual die semiconductor package Grant 8,288,847 - Huang , et al. October 16, 2 | 2012-10-16 |
| Packaging Process to Create Wettable Lead Flank During Board Assembly App 20110244629 - Gong; Zhiwei ; et al. | 2011-10-06 |
| Dual Die Semiconductor Package App 20110175212 - HUANG; Meiquan ; et al. | 2011-07-21 |
| Method Of Packaging Semiconductor Device App 20110165729 - LIU; Peng ; et al. | 2011-07-07 |
| Coated lead frame Grant 7,887,928 - Wang , et al. February 15, 2 | 2011-02-15 |
| Coated Lead Frame App 20090111220 - Wang; Chao ; et al. | 2009-04-30 |
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