Yasui; Takuya

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yasui; Takuya.The latest application filed is for "control device for vehicle, actuator system, control method, non-transitory storage medium, and vehicle".

Company Profile

1.6.12

Yasui; Takuya - Nagoya JP
YASUI; Takuya - Kariya-shi JP
YASUI; Takuya - Nagoya-shi Aichi-ken
Yasui; Takuya - Osaka JP
Yasui; Takuya - Kyoto JP
Yasui; Takuya - Nishikamo-gun JP
Yasui, Takuya - Takatsuki-shi JP
Yasui; Takuya - Takatsuki Osaka 569-1141 JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Vehicle stoppage assistance apparatus Grant 11,420,601 - Yasui , et al. August 23, 2	2022-08-23
Control Device For Vehicle, Actuator System, Control Method, Non-transitory Storage Medium, And Vehicle App 20220118957 - MIYAKE; Kazuki ; et al.	2022-04-21
Travel Control Device App 20210001846 - YASUI; Takuya	2021-01-07
Vehicle Stoppage Assistance Apparatus App 20200223407 - YASUI; Takuya ; et al.	2020-07-16
Antifouling Coating Composition, Antifouling Coating Film Formed By Use Of The Composition, Coated Object Having The Coating Film Thereon, And Method Of Antifouling Treatment By Forming The Coating Film App 20120010342 - Iwamoto; Tsuyoshi ; et al.	2012-01-12
Semiconductor device and semiconductor device layout designing method Grant 8,028,264 - Shimada , et al. September 27, 2	2011-09-27
Method for designing semiconductor integrated circuits having air gaps. Grant 7,698,671 - Fujii , et al. April 13, 2	2010-04-13
Insulating Circuit Board And Insulating Circuit Board Having Cooling Sink App 20090229864 - Kuromitsu; Yoshirou ; et al.	2009-09-17
Wiring Structure Of Semiconductor Integrated Circuit Device, And Method And Device For Designing The Same App 20080197449 - ARAKI; Takayuki ; et al.	2008-08-21
Method And Program For Designing Semiconductor Integrated Circuit, Method And Program For Supporting Design Of Semiconductor Integrated Circuit, And Method And Program For Calculating Wiring Parasitic Capacitance App 20080120583 - Fujii; Tsutomu ; et al.	2008-05-22
Semiconductor device and semiconductor device layout designing method App 20070252258 - Shimada; Junichi ; et al.	2007-11-01
Automatic layout method of semiconductor integrated circuit Grant 7,272,811 - Kurokawa , et al. September 18, 2	2007-09-18
Automatic layout method of semiconductor integrated circuit App 20050155007 - Kurokawa, Keiichi ; et al.	2005-07-14
Semiconductor integrated circuit App 20040183581 - Yasui, Takuya ; et al.	2004-09-23
Delay analysis method and design assist apparatus of semiconductor circuit Grant 6,578,182 - Kurokawa , et al. June 10, 2	2003-06-10
Delay analysis method and design assist apparatus of semiconductor circuit App 20030070151 - Kurokawa, Keiichi ; et al.	2003-04-10
Clock circuit and method of designing the same Grant 6,473,890 - Yasui , et al. October 29, 2	2002-10-29
Delay analysis method and design assist apparatus of semiconductor circuit App 20020010900 - Kurokawa, Keiichi ; et al.	2002-01-24

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.