Yasar; Gulsun
Patent Applications and Registrations
Patent applications and USPTO patent grants for Yasar; Gulsun.The latest application filed is for "method for enhancing a power bus in i/o regions of an asic device".
- Yasar; Gulsun - S. Burlington VT
- Yasar; Gulsun - South Burlington VT
- Yasar; Gulsun - Chittenden VT
- Yasar; Gulsun - Poughkeepsie NY
| Patent | Date |
|---|---|
| Method for enhancing a power bus in I/O regions of an ASIC device Grant 6,598,216 - Chan , et al. July 22, 2 | 2003-07-22 |
| Fast method of I/O circuit placement and electrical rule checking Grant 6,584,606 - Chiu , et al. June 24, 2 | 2003-06-24 |
| Method for enhancing a power bus in I/O regions of an ASIC device App 20030033578 - Chan, Francis ; et al. | 2003-02-13 |
| Method of assigning integrated circuit I/O signals in an integrated circuit package Grant 6,499,134 - Buffet , et al. December 24, 2 | 2002-12-24 |
| Field programmable gate arrays using semi-hard multicell macros Grant 5,761,078 - Fuller , et al. June 2, 1 | 1998-06-02 |
| Method and apparatus for memory dynamic burn-in and test Grant 5,375,091 - Berry, Jr. , et al. December 20, 1 | 1994-12-20 |
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